Automatic P-well clamping for CMOS integrated circuit

Details Automatic P-well clamping for CMOS integrated circuit Automatic P-well clamping for CMOS integrated circuit

1982-07-22

1985-04-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

128419PG, 307571, 307568, H03K 17687, H03K 501, A61M 100

Patent

active

045132127

ABSTRACT:
A fast-operating, minimally complex circuit for automatically clamping the P wells of a CMOS integrated circuit to the most negative potential of the overall circuit. Each of a plurality of N-channel control transistors has its drain connected to a respective one of the circuit nodes whose potential may be the most negative at any given time. The source terminals of all of the control transistors are coupled to a common negative supply bus which is connected to all of the P wells in the integrated circuit. The gates of all of the control transistors are held at a potential which causes them to conduct drain-to-source current. If one of the nodes suddenly drops in potential, the respective control transistor conducts a current in the reverse direction which lowers the potential of the common bus to approximately the potential of the respective node. The respective control transistor conducts heavily until the common bus is thus clamped, and then conducts just enough current to maintain the clamping. Only a single control transistor is required for each node which may determine the most negative potential in the overall circuit. Rapid switching is enhanced by the substrate effect which comes into play when the current reverses direction in one of the control transistors and a large current flows. The same principle applies to integrated circuits containing N wells for P-channel transistors, and of course those containing both N wells and P wells.

REFERENCES:
patent: 4274014 (1981-06-01), Schade, Jr.
patent: 4435652 (1984-03-01), Stevens

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