Automatic on-chip clock tuning methodology and circuitry

Details Automatic on-chip clock tuning methodology and circuitry Automatic on-chip clock tuning methodology and circuitry

1998-04-30

2001-06-12

Vincent, David R. (Department: 3732)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

Reexamination Certificate

active

06246704

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit devices, and more specifically to a method and layout structure for automatic on-chip clock tuning of an integrated circuit device.
There are many instances in which it is desirable to generate a system clock signal on an integrated circuit device. For instance, given an original frequency provided to the integrated circuit device it may be desirable to generate a system clock signal that is double or quadruple the original frequency. The problem arises in tuning the generated system clock signal to a desired duty cycle. The tuning of the duty cycle is typically achieved in a separate tuning exercise subsequent to the generation of the system clock signal. Such tuning of the duty cycle is time-consuming and must normally be repeated each time the frequency of the system clock signal is changed or generated. It would be advantageous in the art to be able to tune the duty cycle of a system clock signal in such a manner that minimizes time and effort. It would further be advantageous in the art to automatically tune a generated system clock signal to a desired duty cycle.
SUMMARY OF THE INVENTION
It is an object of the present invention to automatically tune the duty cycle of a generated system clock signal to a desired duty cycle.
Therefore, according to the present invention, an integrated circuit structure and method capable of automatically tuning the duty cycle of a generated clock signal to any desired value is presented. The tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a series fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.
According to the present invention, a generated clock signal of an integrated circuit device may be automatically tuned to a duty cycle is necessary. A tuning circuit generates one or more select signals that are used to control the duty cycle. The tuning circuit has the following elements: a logic element that performs logic on a high frequency sampling clock signal and a first clock input signal to generate an initial sampling count signal having a pulse width of the first clock signal, a divide counter element that receives and divides the sampling count signal generated by the first logic element by a desired factor to generate a correction signal, and an encoder element that receives the correction signal and generates the one or more select signals. After initial select signals have been generated, the select signals may be adjusted as necessary through a control signal generated from the first clock signal, a second clock signal generated by a first multiplexing circuit and a fourth clock signal generated by a second multiplexing circuit. The control signal is supplied to the logic element of the tuning circuit in lieu of the first clock signal in order to generate a revised correction signal and therefore revised select signals.
A first multiplexing circuit and a second multiplexing circuit, connected in serial fashion, are each provided with the select signals produced by the tuning circuit. The first and second multiplexing circuits each have the same number of serially connected delay elements separated by the same distance from each other and from a multiplexer element. Each delay element is connected to the multiplexer element by a delay path having a delay determined by the predetermined distance between the delay elements. It is important to the proper operation of the invention that the physical layout of the delay elements with regard to each other and the multiplexer element be identical between the first and second multiplexing circuits.
A logic element performs logic on the first clock signal and the second clock output signal of the first multiplexing element to generate the third clock signal. The duty cycle of the third clock signal is automatically changed if necessary by appropriate manipulation of the select signals provided to the first and second multiplexing circuits. A control signal is generated by performing logic on the first, second, and fourth clock signals and this control signal is feed to the logic element of the tuning circuit in lieu of the first clock signals in order to generate a revised sampling control signal. The divide counter element of the tuning circuit receives the revised sampling control signal and generates a revised correction signal. The encoding element in turn generates the revised select signals from the revised correction signal. The revised select signals are supplied to the first and second multiplexing circuit to effect the desired change in the duty cycle of the third clock signal.


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