Automatic multi-banking of memory for microprocessors

Details Automatic multi-banking of memory for microprocessors Automatic multi-banking of memory for microprocessors

1981-08-07

1984-11-06

Ruggiero, Joseph F.

Boots, shoes, and leggings

G06F 1300, G06F 1306

Patent

active

044815700

ABSTRACT:
A microprocessor system is provided with added memories (1-M) to expand its address spaces beyond its address word length capacity by using indirect addressing instructions of a type having a detectable operations code and dedicating designated address spaces of memory to each of the added memories, one space to a memory. By decoding each operations code of instructions read from main memory into a decoder (16) to identify indirect addressing instructions of the specified type, and then decoding the address that follows in a decoder (20) to determine which added memory is associated therewith, the associated added memory is selectively enabled through a unit (22) while the main memory is disabled to permit the instruction to be executed on the location to which the effective address of the indirect address instruction points, either before the indirect address is read from main memory or afterwards, depending on how the system is arranged by a switch (S.sub.1).

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