Automatic logic generation method for pipeline processor

Details Automatic logic generation method for pipeline processor Automatic logic generation method for pipeline processor

1990-03-07

1993-12-28

Lee, Thomas C.

Boots, shoes, and leggings

364488, 364489, 364DIG2, 3649163, 3649446, 36494834, G06F 1520, G06F 1560

Patent

active

052747930

ABSTRACT:
In automatically synthesizing pipeline control, a first circuit indicates the data holding status of a register in response to a circuit description. A second circuit designates the register to receive output of a preceding register in response to the first circuit. A third circuit designates the preceding register to receive input in response to the first circuit without a circuit that indicates the data holding status of the preceding register. Logic responds to: a first file storing circuit description and data propagation behavior; a second file storing register data holding condition and status; and a third file storing logic templates that indicate whether data can be stored by the register, data holding status of the registers, data holding cycles of the registers, and cancel condition of data holding by the registers. The logic templates are assigned for the registers stored in the first file based on the contents of the second file. The element number of the assigned template and mutual connections are defined based on the second file. Based on the second file, determination is made of those registers that may really develop resource conflict among the points where the data meet together and the points where the wait factors of the data transfers develop as well as only those registers which will be affected by the resource conflict. Logic is generated by assigning templates to the thus determined registers, making it possible to suppress the generation of redundant logic.

REFERENCES:
patent: 4816999 (1989-03-01), Berman et al.
patent: 4964056 (1990-10-01), Bekki et al.
patent: 4965758 (1990-10-01), Sherman
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5073855 (1991-12-01), Staplin et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5119495 (1992-06-01), King
patent: 5133069 (1992-07-01), Asato et al.
patent: 5163016 (1992-11-01), Har El et al.

Affiliated with

Also associated with

Rating

Automatic logic generation method for pipeline processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic logic generation method for pipeline processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic logic generation method for pipeline processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1550810