Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-01-03
2002-01-01
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S078000, C327S082000, C327S097000, C327S307000, C327S062000, C375S318000, C375S319000, C330S011000
Reexamination Certificate
active
06335641
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic input threshold selector for digitally controlling a signal with an unfixed amplitude level such as a mouse signal by a one-chip microcomputer.
2. Description of Related Art
A mouse, an input device of a personal computer and the like, includes a light emitting device, a photo-detector and a disk with slits, which is placed between them and rotates in response to the movement of the mouse. The photo-device receives the light emitted from the light emitting device through the disk, and outputs a sinusoidal signal as the disk rotates. The sinusoidal signal is supplied to the one-chip microcomputer or the like to undergo digital processing. The sinusoidal signal, however, has an unfixed amplitude level because of variations in characteristics of the light emitting device and photo-device or of the degradation due to long-term use thereof. Therefore, to achieve accurate digital signal processing of such a sinusoidal signal with an uncertain amplitude level as of the mouse signal, it is necessary to suitably set an input threshold in accordance with the amplitude level of the sinusoidal signal.
FIG. 19
is a schematic diagram showing an arrangement of a conventional automatic input threshold selector. In
FIG. 19
, the reference numeral
21
designates a peak-hold circuit for detecting a maximum value of an input signal IN and for holding it;
22
designates a bottom-hold circuit for detecting a minimum value of the input signal IN and for holding it;
23
designates a voltage comparator for comparing the input signal IN with a reference level VR given as a threshold voltage. The voltage comparator of the automatic input threshold selector receives at its non-inverting input terminal the input signal IN, and at its inverting input terminal the threshold voltage VR generated by dividing with resistors R
1
and R
2
the difference between the maximum voltage output from the peak-hold circuit
21
and the minimum voltage output from the bottom-hold circuit
22
.
Next, the operation of the conventional automatic input threshold selector will be described.
The voltage comparator
23
compares the input signal IN with the reference level VR. If the input signal IN is lower than the reference level VR, it outputs an “L” level signal as its output signal OUT, and if the input signal IN is higher than the reference level VR, it outputs an “H” level signal as the output signal OUT.
With the foregoing structure, the conventional automatic input threshold selector generates the reference level VR by dividing the difference between the maximum voltage and minimum voltage of the input signal held by the peak-hold circuit
21
and bottom-hold circuit
22
. This, however, presents a problem of requiring a rather bulk circuit arrangement and large power consumption, resulting in a cost increase and low performance, considering that the automatic input threshold selector is installed in a semiconductor integrated circuit fabricated by a CMOS process.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide an automatic input threshold selector with a rather small size and low power consumption. This is achieved by selecting an input threshold from a few predetermined levels in response to a compared result of the input signal with predetermined reference levels.
According to one aspect of the present invention, there is provided an automatic input threshold selector comprising: level decision means for deciding, among a plurality of level layers determined by a predetermined number of decision levels, a level layer to which a level of an input signal belongs; and input threshold setting means for selecting, in response to the level layer decided by the level decision means, at least one of input threshold candidates from among a predetermined number of input threshold candidates.
Here, the level decision means may decide, among the plurality of level layers, a level layer to which one of a maximum value and a minimum value of the input signal belongs; and the input threshold setting means may select, in response to the level layer decided by the level decision means, at least one of n input threshold candidates, where n is a natural number.
The level decision means may comprise: a reference level selecting switch for selecting one of the predetermined number of decision levels as a reference level; a first voltage comparator for comparing the input signal with the reference level; a logic gate for carrying out on-off control of a clock signal in response to an output signal of the voltage comparator; a shift register for shifting, in response to an output signal of the logic gate, its output state every time the input signal crosses the reference level in one of rising and falling directions of the input signal; and a decoder for outputting signals for identifying the level layer of the input signal in response to output signals of the shift register, wherein the reference level selecting switch may select the reference level in accordance with the output signals of the decoder, the input threshold setting means may comprise: the decoder; and an input threshold selecting switch for selecting, in response to the outputs of the decoder, one of the n input threshold candidates as the input threshold, and the automatic input threshold selector may further comprise a second voltage comparator for comparing the input signal with the input threshold.
The level decision means may comprise: maximum value level decision means for deciding, among (j+1) level layers determined by j maximum value decision levels, a level layer to which a maximum value of the input signal belongs, where j is a natural number; and minimum value level decision means for deciding, among (m+1) level layers determined by m maximum value decision levels, a level layer to which a minimum value of the input signal belongs, where m is a natural number, wherein the input threshold setting means may set the input threshold by selecting one of the input threshold candidates in response to the level layer decided by the maximum value level decision means and to the level layer decided by the minimum value level decision means.
The input threshold setting means may comprise: a first input threshold selecting switch for selecting, in response to the level layer decided by the level decision means, one of the n input threshold candidates as a first input threshold; and a second input threshold selecting switch for selecting, in response to the level layer decided by the level decision means, another one of the n input threshold candidates as a second input threshold, and the automatic input threshold selector may further comprise Schmitt circuit means for comparing the input signal with the first input threshold when the input signal is rising, and with the second threshold when the input signal is falling.
The level decision means may comprise: maximum value level decision means for deciding, among (j+1) level layers determined by j maximum value decision levels, a level layer to which a maximum value of the input signal belongs, where j is a natural number; and minimum value level decision means for deciding, among (m+1) level layers determined by m maximum value decision levels, a level layer to which a minimum value of the input signal belongs, where m is a natural number, the input threshold setting means may comprise: first input threshold setting means for setting a first input threshold by selecting one of predetermined n
1
first input threshold candidates in response to the level layer decided by the maximum value level decision means, where n
1
is a natural number; and second input threshold setting means for setting a second input threshold by selecting one of predetermined n
2
second input threshold candidates in response to the level layer decided by the minimum value level decision means, where n
2
is a natural
Cunningham Terry D.
Mitsubishi Electric System LSI Design Corporation
Nguyen Long
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