Multiplex communications – Diagnostic testing
Reexamination Certificate
1999-02-12
2002-12-10
Yao, Kwang Bin (Department: 2664)
Multiplex communications
Diagnostic testing
Reexamination Certificate
active
06493320
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to network systems, and more particularly to an apparatus and method for automatically initializing, tuning, and testing a plesiochronous, parallel link to achieve improved link performance.
BACKGROUND OF THE INVENTION
Links (i.e., interconnects) are used for transmitting data between routers in a network. Components that are used for forming links include, for example, integrated circuits, packaging for integrated circuits, printed circuit boards, connectors, cables, drivers, receivers, and other components. The characteristics and dimensions of link components vary, and as a result, can affect link performance. These variations may be due to the variations inherent in manufacturing processes. Acceptable components typically have variations that fall within rigidly-set manufacturing tolerances. Components that fall beyond the predetermined manufacturing tolerances are discarded.
As one example, a printed circuit board may be used as part of a link. The characteristics of the link are affected by the lengths/shapes of the traces on the printed circuit board, the quality of the board, and other factors that are influenced by the variations in manufacturing processes. Thus, the performance of different links may vary, since the characteristics of different circuit boards may vary.
The characteristics of link components may also vary based upon the particular network implementation or design. For example, longer-length links (in a particular implementation) require more power to drive signals across the links.
Additionally, the skew of the signal arrival time (at a receiving end of the link) for parallel signals increases as link components vary in length and/or characteristics. Typically, the skew is greater for longer-length parallel conductors than for shorter-length parallel conductors. As a result of greater skew, the signals along the parallel conductors will have different arrival times at the receiving end of the parallel conductors.
Accordingly, it is desirable to provide a method and apparatus that automatically compensates for the different component characteristics that are due to variations in the manufacturing processes and/or particular design implementations. It is further desirable to provide a method and apparatus that maximizes signal transmission across a link, while minimizing the power level that is required for signal transmission. It is further desirable to provide a method and apparatus that sets appropriate operating margins in the link to achieve sustained and reliable operation across the link. It is further desirable to provide an apparatus and method that compensates for variations in the manufacturing processes, thereby leading to a reduction in the number of components that are discarded due to rigidly-set manufacturing tolerances.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for automatically initializing and tuning a link in a network system. The link is used for coupling one router to another router and may be implemented as a high speed, plesiochronous, parallel link. The apparatus in accordance with the present invention comprises a first link control unit coupled to a first end of the link; and a second link control unit coupled to a second end of the link and capable of communicating with the first link control unit to achieve automatic adjustment of at least some parameters of the link to improve performance of the link. According to an aspect of the present invention, the link control units are each state machines implemented in digital hardware.
The link control units communicate with each other to initialize, tune, and test the link. Communications between the link control units are performed in-band and at slow speed. Additionally, the link control units can communicate with each other even if the parameters of the drivers and receivers in the link are minimally tuned.
As a result of the tuning procedure performed in accordance with the present invention, data transmission can occur across the link at the fastest possible speed and at the lowest possible power level. In addition, the tuning procedure permits the setting of appropriate voltage margins in the receivers in the link to achieve sustained and reliable operations across the link. These voltage margins compensate for noise, power supply voltage variations, temperature variations, and/or other network environmental changes that may affect the timing and/or magnitude of signals that propagate across the link.
According to another aspect of the present invention, the following parameters are among the parameters that may be adjusted in a link:
(1) the terminator resistance on each end of the link;
(2) the DC current level of a driver circuit in the link wherein the DC current is used for maintaining a static signal on the link;
(3) the AC current level of a driver circuit in the link wherein the AC current enables the high-to-low or low-to-high transitions of a signal on the link;
(4) the transmission speed of a signal across the link;
(5) the phase relationship between a receiver clock and incoming data signals on each end of the link; and
(6) the relative delay between individual data lines in the link, in order to reduce any skew between parallel data bits that arrive on each end of the link.
To determine the appropriate parameter settings for the link, known stimuli are transmitted across the link and are subsequently measured on both ends of the link. The known transmitted stimuli include reference voltages and conventional tuning patterns. The stimuli measurement methods include comparing the detected signal voltage levels with known voltage reference levels, comparing the timing of signal transitions with known reference timing signals, and comparing the received signal patterns on each end of the link with known reference patterns.
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Delbert Cecchi, et al., “A 1.0 GB/Second SCI Link in 0.8&mgr; BiCMOS”, IBM Corporation, System Technology and Architecture Division, Rochester, MN, pp. 1-24, Mar. 21, 1995.
Hayes, T. C., Horwitz, P., “Student Manual for the Art of Electronics,” Cambridge University Press, Chapter 9, pp. 406-430, 1989.
Horowitz, P., Hill., W., “The Art of Electronics,” Cambridge University Press, Second Edition, Chapter 9, pp. 641-655, 1989.
Gotoh Kohtaro
Koyanagi Yoichi
Sastry Raghu
Schober Richard L.
Tamura Hirotaka
Fenwick & West LLP
Jones Prenell
Yao Kwang Bin
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