Automatic IIP2 calibration architecture

Details Automatic IIP2 calibration architecture Automatic IIP2 calibration architecture

2007-01-25

2010-06-22

Nguyen, Lee (Department: 2618)

Telecommunications

Transmitter

Having harmonic radiation suppression

C455S295000, C455S296000

Reexamination Certificate

active

07742747

ABSTRACT:
An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

REFERENCES:
patent: 7340234 (2008-03-01), Jun et al.
patent: 7561862 (2009-07-01), Woo-nyun
patent: 2006/0073803 (2006-04-01), Igarashi et al.
patent: 0 473 373 (1992-03-01), None
patent: 1 067 675 (2001-01-01), None
patent: WO 03/065602 (2003-08-01), None

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