Communications: electrical – Digital comparator systems
Reexamination Certificate
2000-12-15
2002-07-16
Wambach, Margaret R. (Department: 2816)
Communications: electrical
Digital comparator systems
Reexamination Certificate
active
06420962
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver. More particularly, the present invention relates to an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver, capable of automatically controlling an identification level or an identification timing according to an input signal.
2. Description of the Related Art
In a high-speed long-distance optical transmission, an optical signal is subject to a waveform distortion due to characteristics of a fiber (e.g., a band reduction, a non-linear effect). Therefore, the optimal position of the identification level for the optical signal is constantly changing. At present, however, since the identification level is fixed to a single point, the identification level is not set to the optimal identification level for various conditions. A resulting drawback is a narrow error margin which may limit the transmission distance.
In view of such a problem in the prior art, methods for controlling an identification level or an identification phase have been proposed in the art.
For example, Japanese Laid-Open Patent Publication No. 08-265375 discloses a method for controlling an identification level and a method for controlling an identification phase. In the method for controlling the identification level, a comparison is made between two output signals of adjacent levels among three output signals from three identifiers which receive a data input and have respectively different identification levels (i.e., low, intermediate and high levels). For example, the high level output signal is compared with respect to the intermediate level output signal. If the comparison result indicates a mismatch, the three identification levels are parallelly (i.e., with the intervals therebetween kept unchanged) shifted toward a direction opposite to the identification level used in the comparison (e.g., the high level). For example, if a result indicating a mismatch occurred between the intermediate level and the high level, the three identification levels are parallelly shifted to lower levels, respectively. In the method for controlling the identification phase disclosed in this laid-open patent publication, a comparison is made between two output signals of adjacent timings among three output signals from three identifiers which receive a data input and have respectively different identification timings (i.e., delayed, intermediate and advanced phases). For example, the advanced phase output signal is compared with respect to the intermediate phase output signal. If the comparison result indicates a mismatch, the three identification timings are parallelly shifted toward a direction opposite to the identification timing used in the comparison (e.g., the advanced phase). For example, if a result indicating a mismatch occurred between the intermediate phase and the advanced phase, the three identification timings are parallelly shifted to more delayed timings, respectively.
However, the above-described conventional method has the following problems.
In the method for controlling an identification level or an identification phase described in Japanese Laid-Open Patent Publication No. 08-265375, supra, although all of the three identification levels or identification timings used for the control are parallelly shifted, the intervals therebetween are fixed. Therefore, the control system may be instable when the difference between high and low levels of the incoming signal decreases. Specifically, when the high identification level of the three identification levels is optimized, the low identification level may become less than the low level of the signal, resulting in a “mismatch” result from a comparison with respect to the output of the identifier of the intermediate identification level. Then, if the low identification level is optimized, the high identification level deviates from the optimal value. Therefore, the control system as a whole may not reach a stable state, whereby even an oscillation may occur.
An object of the present invention is to solve the above-described problem by providing an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver, capable of stably setting an identification level or an identification phase.
SUMMARY OF THE INVENTION
In order to achieve the above-described object, an automatic identification level control circuit of the present invention comprises: a plurality of identification circuits receiving an input data signal and having identification levels different from one another; a plurality of exclusive OR circuits each outputting a match determination signal indicating “match” or “mismatch” between outputs from the identification circuits which respectively correspond to two identification levels adjacent to each other in terms of magnitude among the identification levels different from one another; and an identification voltage control circuit for outputting a control signal for adjusting respective absolute values of the identification levels different from one another and an interval therebetween so that the match determination signal indicates “match”.
An automatic identification level control circuit of the present invention may comprise: a plurality of identification circuits receiving an input data signal and having identification levels different from one another; a plurality of exclusive OR circuits each outputting a match determination signal indicating “match” or “mismatch” between outputs from the identification circuits which respectively correspond to two identification levels adjacent to each other in terms of magnitude among the identification levels different from one another; and an identification voltage control circuit for outputting a control signal for adjusting a difference between a DC level of the input data signal and one of the identification levels different from one another, and each of the other identification levels so that the match determination signal indicates “match”.
The identification voltage control circuit may comprise: a charging circuit whose output voltage is incremented when a first one of the match determination signals corresponding to a first one of the identification levels indicates “mismatch”; a discharging circuit whose output voltage is decremented when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates “mismatch”; and a charging/discharging circuit having a first output whose voltage rapidly decreases when at least one of the first and second match determination signals indicates “mismatch” and gradually increases when both of the first and second match determination signals indicate “match”, and a second output whose voltage rapidly increases when at least one of the match determination signals indicates “mismatch” and gradually decreases when both of the match determination signals indicate “match”.
The identification voltage control circuit may comprise: a discharging circuit whose output voltage is decremented when a first one of the match determination signals corresponding to a first one of the identification levels indicates “mismatch”; a charging circuit whose output voltage is incremented when a second one of the match determination signals corresponding to a second one of the identification levels which is less than the first identification level indicates “mismatch”; and a charging/discharging circuit having a first output whose voltage rapidly decreases when at least one of the first and second match determination sig
Honma Yoshinori
Kawano Toshibumi
Kobayashi Hirokazu
Kuriyama Takashi
Matsumoto Yoshihiro
McGinn & Gibb PLLC
NEC Corporation
Wambach Margaret R.
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