Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2006-09-12
2006-09-12
Ferris, Fred (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S014000, C703S002000, C716S030000, C716S030000
Reexamination Certificate
active
07107198
ABSTRACT:
A tool for automatically generating a reduced size circuit model including inductive interaction properties is provided. Such inclusion of inductive properties in the reduced size circuit model allows for a more complete and accurate circuit model than those created by conventional methods. Further, a technique for automatically generating a reduced size circuit model including inductive properties that uses less memory space and operates faster than conventional methods is provided.
REFERENCES:
patent: 6023573 (2000-02-01), Bai et al.
patent: 6031986 (2000-02-01), Milsom
patent: 6063130 (2000-05-01), Sakamoto
patent: 6088523 (2000-07-01), Nabors et al.
patent: 6134513 (2000-10-01), Gopal
patent: 6308304 (2001-10-01), Devgan et al.
patent: 6324493 (2001-11-01), Belk
patent: 6367053 (2002-04-01), Belk et al.
patent: 6397171 (2002-05-01), Belk
patent: 6453444 (2002-09-01), Shepard
patent: 6467078 (2002-10-01), Matsuba et al.
patent: 6662149 (2003-12-01), Devgan et al.
patent: 6870436 (2005-03-01), Grebenkemper
patent: 2003/0069722 (2003-04-01), Beattie et al.
“Delivering a Full-chip Hierarchical Circuit Simulation & Analysis Solution for naonmeter Designs”, S. Wang et al, White Paper, Nassada Corp. Feb. 2001.
“Interconnect Electromagnetic Modeling using Conduction Modes as Global Basis Functions”, L. Danial et al, IEEE 0-7803-6450-3/00, IEEE 2000.
“Measurement and Modeling of On-chip Transmission Line Effects in a 400 MHz Microprocessor”, Restle et al, IEEE Jouranl o Solid-State Circuits, vol. 33, No. 4, Apr. 1998.
“FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program” IEEE Transactions on Computer-Aided Design, vol. 10, No. 11, Nov. 1991 Authors Keith Nabors and Jacob White, Associate Member, IEEE.
“GMRES: A Generalized Minimal Residual Algorithm for Solving Nonsymmetric Linear Systems” Society for Industrial and Applied Mathematics, vol. 7, No. 3, Jul. 1986 Authors Youcef Saad and Martin H. Schultz.
“Heirarchical Interconnect Circuit Models” Michael Beattie, Satrajit Gupta and Lawrence Pileggi Carnegie Mellon University Department of Electrical and Computer Engineering 5000 Forbes Avenue, Pittsburgh, PA 15213.
“PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm” Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi Department of Electrical and Computer Engineering Carnegie Mellon University, Pittsburgh, PA 15213.
S. Kapur and D. Long, “IES3: A Fast Integral Equation Solver for Efficient 3-Dimensional Extraction”, Proceedings of the ICCAD '97 (7 pages).
M. Kamon, J. J. Tsuk and J. K. White, “FASTHENRY: A Multipole-Accelerated 3D Inductance Extraction Program”, IEEE Trans MTT-42, Sep. 1994, pp. 1750-1758 (28 pages).
LandOfFree
Automatic generation of reduced-size circuit models... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic generation of reduced-size circuit models..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic generation of reduced-size circuit models... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3529310