Automatic generation of code for component interfaces in models

Details Automatic generation of code for component interfaces in models Automatic generation of code for component interfaces in models

2011-03-22

2011-03-22

Yigdall, Michael J (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Code generation

C717S120000, C717S124000, C717S135000, C710S008000, C703S013000, C703S022000

Reexamination Certificate

active

07913222

ABSTRACT:
Methods, systems and computer program products are disclosed for automatically generating hardware description language code from a model. The hardware description language code may be generated from a graphical program/model, such as a block diagram model. The hardware description language code may also be generated from a text-based program/model, such as a model created using MATLAB® tools. In particular, the present invention provides for the automatic code generation of an interface between components in the model. The present invention may provide options for selecting at least one of multiple types or styles of the component interfaces in the model. The selection of the interface types or styles may be controlled by the user or inferred by other parameters, such as implementation parameters.

REFERENCES:
patent: 6058263 (2000-05-01), Voth
patent: 6553554 (2003-04-01), Dahl et al.
patent: 6564363 (2003-05-01), Dahl et al.
patent: 6718421 (2004-04-01), Conroy
patent: 7272546 (2007-09-01), Brown et al.
patent: 2003/0195732 (2003-10-01), Kodosky et al.
patent: 2005/0216247 (2005-09-01), Ikeda et al.
patent: 2008/0141227 (2008-06-01), Waters et al.
Wingard et al., “Integration Architecture for System-on-a-Chip Design”, 1998 IEEE, pp. 85-88 (International Search Report—PCT/US2005/033848).
Choi et al., “Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software”, 1999 ACM, pp. 939-944 (International Search Report—PCT/US2005/033848).
D'silva, “Bridge Over Troubled Wrappers: Automated Interface Synthesis”, 2004 IEEE, pp. 1-6 (International Search Report—PCT/US2005/033848).
Choi et al., “Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software”, 1999 ACM, pp. 939-944.
Matthias Gries, “Methods for evaluating and covering the design space during early design development”, Jun. 3, 2004, Elsevier, pp. 131-183.
Donno et al., “Power-Aware Clock Tree Planning”, Apr. 18, 2004, ACM, pp. 138-147.
Donno et al., “Clock-Tree Power Optimization based on RTL Clock-Gating”, Jun. 2, 2003, ACM, pp. 622-627.
Choi, Hoon et al, “Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software,” Design Automation, 1999. 36th Annual Conference on New Orleans, LA, USA Jun. 21-25, 1999, Piscataway, NJ, USA, IEEE, pp. 939-944.
D'Silva, Vijay et al, “Bridge Over Troubled Wrappers: Automated Interface Synthesis,” VLSI Design, 2004, Proceedings, 17th International Conference on Mumbai, India, Jan. 5-9, 2004, Los Alamitos, CA, USA, IEEE Comput. Soc. U.S., pp. 189-194.
Wingard, Drew et al, “Integration Architecture for System-on-a-Chip Design,” Custom Integrated Circuits Conference. Proceedings of the IEEE Santa Clara, CA, USA May 11-14, 1998, New York, NY, USA, IEEE, US, pp. 85-88.
International Search Report for Application No. PCT/US2005/033848, dated Apr. 21, 2006.

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