Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation
Reexamination Certificate
2001-08-29
2002-12-24
Trost, William (Department: 2683)
Telecommunications
Receiver or analog modulated signal frequency converter
Local control of receiver operation
C455S247100, C455S251100, C455S253200, C455S234200, C455S324000, C330S133000, C330S278000
Reexamination Certificate
active
06498927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a circuit and method for gain control, and in particular to a circuit and method for gain control in wireless or wired communication systems.
2. Background of the Related Art
FIG. 1
illustrates a wireless receiver conceptually divided into two major sections being an analog front-end and a base-band digital signal processor (DSP). As shown in
FIG. 1
, in a receiver
100
an analog front-end
106
receives a modulated signal through an antenna
102
, amplifies the modulated signal and down-converts the modulated signal directly to a low frequency
108
or through a suitable intermediate frequency (IF). The low frequency analog signal
108
is converted to digital bits by an analog-to-digital converter and goes to the base-band DSP section
110
for demodulation and further digital processing. An output
112
of the DSP section
110
is received by a user.
The analog front-end generally needs good sensitivity to detect the desired signal despite a weak signal strength and a linearity. Among different types of architectures used in radio frequency integrated circuits (RF ICs), the direct conversion architecture, also known as homo-dyne, has advantages for low-power applications.
FIG. 2
shows a block diagram of a related art direct conversion receiver
200
. The direct conversion receiver
200
is important because it can accomplish channel selection filtering by processing within a chip, which helps to reduce the number of off-chip components, and thereby achieve better miniaturization. As shown in
FIG. 2
, the related art direct conversion receiver
200
is a highly integrated receiver that includes an antenna
202
that is connected to a low noise amplifier (LNA)
210
through a duplex filter
206
. The LNA
210
has an output
212
that is respectively fed into a first mixer
216
and a second mixer
218
. A serial programming interface
220
receives an input
223
from outside the direct conversion receiver
200
, and also receives an output
229
from a crystal oscillator
227
. The serial programming interface
220
outputs a channel setting
224
to a frequency synthesizer
228
. A clock generator
222
also receives an input
225
from the crystal oscillator
227
and outputs a reference clock
226
to the frequency synthesizer
228
. The frequency synthesizer
228
is made up of a PFD
232
, a loop filter
230
, a prescaler
234
, and a voltage-controlled oscillator (VCO)
236
. An output
240
of the frequency synthesizer
228
is received by a phase shifter
244
. The phase shifter
244
has a +45° output
246
fed into the mixer
216
and a −45° output
248
fed into the second mixer
218
.
In the related art direct conversion system
200
, a desired RF signal passing the duplex filter
206
and amplified by the LNA
210
is directly down converted by the mixer
216
because a local oscillator (LO) frequency
246
, which is the phase shifted signal
240
from the frequency synthesizer
228
, is equal to a carrier frequency of the desired RF signal. The down converted signal
250
is amplified by the variable gain amplifier (VGA)
252
before the base band (BB) filter
256
to get the amplitude large enough to overcome the large noise floor of the BB low pass filter
256
before the analog-to-digital converter (ADC)
260
, which outputs one channel
280
(e.g., in-phase channel I) of the direct conversion receiver
200
. A mixer
218
, a VGA
266
, a BB filter
270
and an ADC
274
operate to output a second channel
276
(e.g., quadrature-phase channel Q) of the direct conversion receiver
200
.
The simplicity of the direct conversion architecture offers two important advantages over superheterodyne architecture. First, the problem of generation of images is circumvented because an intermediate frequency (IF) in the superheterodyne receiver is baseband (i.e., F
IF
=0) in the direct conversion receiver. As a result, no image filter is required and the LNAs do not have to drive a 50-ohm load. Second, the IF SAW filter and subsequent down-conversion stages can be replaced with low-pass filters and baseband amplifiers, both of which can be easily implemented in a single chip.
However, the related art direct conversion receivers have disadvantages for high performance radio receivers. First, rejection of out-of-channel interferers with an active low-pass filter is more difficult than with a passive filter because active filters exhibit much more severe noise-linearity-power trade-offs than do their passive filter counterparts. However, several related art topological candidates for baseband circuits will now be described.
As shown in
FIG. 3
, an input
302
for a related art baseband circuit
300
a
is then transmitted to a low-pass BB filter
304
that suppresses out-of-channel interferers, thereby allowing a series connected amplifier
308
to be a nonlinear, high-gain VGA amplifier. The low-pass filter
304
further allows an ADC
312
to have a moderate dynamic range. However, the low-pass filter
304
preceding the amplifying stages imposes tight noise-linearity trade-offs in the baseband circuit
300
a.
An output
314
of the ADC
312
is the output of the baseband structure.
As shown in
FIG. 3
, a second related art baseband circuit
300
b
relaxes the LPF noise requirements while demanding a higher performance in the amplifier. In the baseband circuit
300
b,
an input
316
is initially fed into a VGA
318
, and an amplified signal
320
of the VGA
318
is received by a low-pass BB filter
322
. An output
324
of the BB filter
322
is received by an ADC
326
. The ADC
326
has an output
328
that is the output of the second baseband structure.
As shown in
FIG. 3
, a third related art baseband circuit
300
c
demonstrates the use of channel filtering in the digital domain. In the baseband circuit
300
c,
an input
330
is fed into a VGA
332
, and an output
334
of the VGA
332
is received by an ADC
336
. A BB filter
340
receives an output
338
of the ADC
336
. An output
342
of the BB filter
340
is the output of the third baseband circuit
300
c.
In the third baseband circuit
300
c,
the ADC
336
must achieve both a high degree of linearity so as to digitize the signal with minimal intermodulation of interferers, as well as exhibit a thermal and quantization noise floor well below the signal level.
As described above, trade-offs required by the individual baseband structures shown in
FIG. 3
are alleviated by combining the above methods, so that amplification and filtering are distributed to several gain and filter stages, which optimizes the performance. In modern communication systems, the required channel filtering must exceed 60 dB in order to reject interferers in nearby channels. Also, the required signal gain must exceed 70 dB. The implementation of baseband circuits without external passive elements are quite difficult, regardless of any configuration shown in
FIG. 3
, because the front-end stage has too severe dynamic range requirements. However, the dynamic range requirements of individual elements of a baseband circuit can be relaxed by employing several gain and filtering stages in series.
FIG. 4
is a block diagram that shows a related art direct conversion receiver. As shown in
FIG. 4
, a direct conversion receiver
400
includes a baseband circuit
420
with a plurality of amplifiers and filters. However, the specific configuration of the baseband circuit
420
can be modified depending on system requirements.
As shown in
FIG. 4
, an RF signal is received by an antenna
402
and filtered by a duplex filter
406
, and a filtered signal
408
is amplified by a LNA
410
. The filtered amplified signal
412
is down converted to a baseband signal by a local oscillator (LO) signal
416
in a mixer
414
. Within the baseband circuit
420
, an output
418
from the mixer is variously amplified and filtered before being output to an ADC
442
. As shown in
FIG. 4
, the baseband circuit
420
uses a first VGA
422
, a
Kang Suwon
Lee Jeong-Woo
Park Joonbae
Fleshner & Kim LLP
GCT Semiconductor Inc.
Perez-Gutierrez Rafael
Trost William
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