Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit
Utility Patent
1997-09-22
2001-01-02
Faber, Alan T. (Department: 2753)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Head amplifier circuit
C360S067000, C360S065000, C330S254000
Utility Patent
active
06169638
ABSTRACT:
TECHNICAL FIELD
This invention relates to data processing apparatus and methods, and to electronic circuits for use in connection therewith. In particular, but not exclusively, the invention relates to apparatus and methods for retrieving data stored using a DDS Data Storage System. The invention also extends in general to apparatus and methods for processing data in one or more communications channels.
BACKGROUND ART
It is already known to provide reliable storage and retrieval of large volumes of digital data, such as computer data, in particular by means of the DDS (Digital Data Storage) format defined in ISO/IEC standard 12247.
In a DDS read/write mechanism using the above format, data are recorded on an elongate recording media, comprising a tape coated with a magnetic medium, by a rotating drum carrying one or more electromagnetic heads. The tape is moved by a motor-driven capstan along a path extending between two spools or reels and wrapped partially around the drum. The plane of rotation of the heads of the drum is disposed at an angle to the plane of movement of the tape, so that each head traverses the tape along successive tracks extending across the width of the tape at an angle to its centre line. The mechanism includes appropriate circuitry for encoding data into signals suitable for recording onto tape, including error-detection and correction codes, and for conditioning of those signals into a form which is optimally matched to the characteristics of the recording media. For data retrieval, additional circuitry is provided for detecting magnetic field variations stored on the tape, deriving corresponding signals, conditioning those signals into a form suitable for subsequent processing, decoding the encoded data and detecting and correcting errors.
In a current format (DDS-2), data are recorded at a bit density of approximately 61 kilobits per inch (kbpi) (equivalent to approximately 24 kilobits per centimetre) At this bit density, a typical DDS tape cartridge can currently store up to approximately 8 gigabytes of data, using the longest practicable tape and techniques such as data compression to maximise the quantity of data the tape can accommodate. With the steadily increasing use of computer equipment and the volumes of data processed and stored by such equipment, it has become desirable to increase the capacity of a DDS tape cartridge still further.
We are in the process of developing a new format (DDS-3) which further increases the storage capacity by doubling the linear recording density and increasing the proportion of a recorded track that is available for user data. Together, these improvements are estimated to provide about three times the data capacity of DDS-2, for a cartridge of given tape length. The DDS-3 format, when recorded on the longest practicable tape, is designed to provide a storage capacity of 12 gigabytes of uncompressed user data or typically 24 gigabytes of compressed user data.
Reference is directed to our earlier published International Patent Application WO95/15551 for further details of this scheme, the contents of the earlier Patent Application being incorporated herein by reference.
Because the linear bit density in DDS-3 is twice that of DDS-2, the bit spacing on the tape is approximately one half of the gap of the preferred read head. This means that the output signal from the read head, instead of varying between two discrete levels (+1,−1) will vary between three (+2,0,−2), and as such, DDS-3 will be a 3-level system.
It is proposed to recover recorded data by means of a partial-response maximum-likelihood (PRML) data recovery channel.
“Partial Response” denotes a practicable Partial Response signalling scheme which only requires up to the Nyquist frequency bandwidth for data transmission, by enforcing deterministic intersymbol-interference at the detector input. An example is the PR-1 (or duobinary) Partial Response system (recording channel transfer function) which is described by the discrete time transfer function F(D)=D+1. Other examples such as class IV or PR-4 exist, and we do not exclude these possibilities.
“Maximum Likelihood” denotes a Maximum Likelihood Detection decoding scheme, implementing a Viterbi algorithm, which chooses the most likely sequence of output data, using a sequence of received samples, instead of just one received sample at a time.
In the read-mode of a typical proposed scheme for DDS-3, the approximately equalised signal is taken and is subjected to Automatic Gain Control to establish and stabilise the signal amplitudes, and then to full Adaptive Equalisation to a combined PR-1 target. In the Adaptive Equalisation step, an adaptive, sampled finite impulse response filter is used to provide a three-level PR-1 target transfer function. In one embodiment, after Adaptive Equalisation, the signal undergoes analogue to digital conversion, followed by three-level Viterbi (or Maximum Likelihood) detection. In order to do this, clock information is extracted from the input signal and used to synchronise the Adaptive Equaliser, the analogue to digital converter, and the Viterbi decoder. In another embodiment, the Adaptive Equalisation may instead be performed after analogue to digital conversion.
As in previous DDS formats, in the proposed DDS-3 format, data is stored as a series of tracks of alternate azimuth (referred to as the A track and B track respectively). Each end of each track is occupied by a margin region which is expendable, the front margin being followed by a preamble region, which is often indistinguishable from the margin. The preamble region is normally a plain sinusoidal tone and does not carry any data, but exists to enable the AGC loop and the clock recovery loop to achieve fast lock-on and also to identify the start of the main data region. A preamble detector controls the Adaptive Equaliser to ensure that the channels do not try to adapt the preamble or margin regions, because otherwise they will not be optimised for the data portion.
In this Specification, the term communications channel is used broadly to include channels of data retrieved from a recorded medium.
SUMMARY OF THE INVENTION
For stable operation of the Viterbi detector and the Adaptive Equaliser, the gain in the signal should not vary outside preset limits. Ideally, the absolute gain and the relative gain in the signal is less than 1% for the Viterbi detector, although it is tolerant of slightly greater variation in absolute gain. The Adaptive Equaliser is not so demanding but still typically requires the offset gain to be less than 10% and the relative gain to be less than 1%.
We have found that a conventional automatic gain control loop using peak detection may introduce a gain step at the interface between the preamble and main data regions due to their varying spectral characteristics, and this could be interpreted incorrectly downstream as a change in signal level.
Certain gain control systems exist which use a peak detector to make a coarse adjustment of the gain and then examine individual bits to effect fine adjustment. These types of system are data driven and prone to collapse if the clock recovery is disturbed.
We have developed a gain control system which is more robust as it does not require recovery of the clock signal. Furthermore, in a preferred system, a common simple peak detector may be used, even though the margin/preamble and main data regions have different spectral characteristics.
Accordingly, in one aspect of this invention, there is provided an automatic gain control circuit for automatic gain control of an input signal comprising a first signal region followed by a second signal region, which circuit comprises:
variable gain amplifier means for receiving and amplifying said input signal;
a gain control loop responsive to the output of said amplifier means and to respective target values for said first and second signal regions to control the gain applied by said amplifier means,
target control means for monitoring the gain applied for each of said firs
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