Patent
1974-12-23
1976-01-20
Claffy, Kathleen H.
179 15BL, H04J 302
Patent
active
039340910
ABSTRACT:
Port circuits in a time division switching system that have their outputs connected to a common summing bus by respective summing resistors have their output signals attenuated when the conversation is among port circuits on the same bus: the simultaneous closure of the respective time slot switches causes the summing resistor of one port to shunt the output from the other port. However, when the connection involves port circuits served by different summing buses, there is usually sufficient isolation between the buses to mask the shunting effect. The present disclosure shows an arrangement for selectively adding a compensating amplifier and an attenuating resistor to each distribution bus. When the call involves port circuits served by the same summing and distribution bus pair the amplifier completely compensates for all attenuation. When the call involves ports served by a different summing and distribution bus pair, there is no input shunting to reduce gain but now a pair of compensating amplifiers are involved and their input attenuating resistors are in shunt to ground reducing the gain to the normal level.
REFERENCES:
patent: 3761624 (1973-09-01), Lewis et al.
Bell Telephone Laboratories Incorporated
Claffy Kathleen H.
Kemeny E. S.
Popper H. R.
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