Automatic frequency control circuit

Details Automatic frequency control circuit Automatic frequency control circuit

2000-06-23

2003-05-27

Trost, William (Department: 2683)

Telecommunications

Receiver or analog modulated signal frequency converter

Signal selection based on frequency

C455S164100, C455S182100, C455S182300, C455S192100, C455S192200

Reexamination Certificate

active

06571088

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to an AFC (Automatic Frequency Control) circuit for matching the frequency of a reference clock signal in a mobile station to the frequency of a reference clock signal in a base station as a transmitting side.
In recent years, as a communication system used in mobile communication, attention is directed to a CDMA (Code Division Multiple Access) communication system resistant against interference and disturbance. In the CDMA communication system, communication is carried out as follows. On a transmitting side, a user signal to be transmitted is spread by the use of a spread code before it is transmitted. On a receiving side, despreading is carried out by the use of a spread code identical with the above-mentioned spread code to obtain the original user signal.
In the above-mentioned CDMA communication system, it is impossible to carry out despreading on the receiving side unless phase synchronization is established between spread code sequences on the transmitting side and the receiving side. Under the circumstances, in a mobile station as the receiving side, a TCXO (Temperature Compensated Crystal Oscillator) having very high frequency accuracy is used as a reference oscillator. The reference oscillator serves to generate a reference clock signal used upon demodulating a reception signal supplied from a base station as the transmitting side. However, since the mobile station is required to be small in size and low in cost, the reference oscillator used in the mobile station is relatively low in frequency accuracy as compared with that used in the base station. In this connection, the mobile station carries out an AFC operation for matching the frequency of the reference clock signal in the mobile station to the frequency of a reference clock signal in the base station.
Referring to
FIG. 1
, a conventional AFC circuit for carrying out the above-mentioned AFC operation will be described. The conventional AFC circuit is formed by a heterodyne receiver and comprises an antenna
1
, a low-noise amplifier (LNA)
2
, a down converter
3
, an AGC (Automatic Gain Control) amplifier
4
, a quadrature demodulator (DEM)
5
, an A/D (Analog-to-Digital) converter
6
, a PLL (Phase-Locked Loop) circuit
7
, a reference clock generating circuit (TCXO)
8
, an accumulator
9
, a demodulating circuit
10
, a frequency offset estimating circuit
51
, a delay profile/search circuit
12
, a CPU (Central Processing Unit)
53
, and a timing generating circuit
54
.
The low-noise amplifier
3
amplifies a reception signal received through the antenna
1
from a base station
300
. The low-noise amplifier
3
thereby produces an amplified signal. The down converter
3
is supplied with the amplified signal from the low-noise amplifier
3
and converts the amplified signal into an intermediate frequency (IF) signal by the use of a first local signal
16
1
. The AGC amplifier
4
is supplied with the IF signal from the down converter
3
and carries out gain control of the IF signal so that the A/D converter
6
has a constant input level. The AGC amplifier
4
delivers a gain-controlled IF signal to the quadrature demodulator
5
.
Supplied with the gain-controlled IF signal, the quadrature demodulator
5
carries out quadrature demodulation by the use of a second local signal
162
to convert the gain-controlled IF signal into an analog baseband signal. Supplied with the analog baseband signal from the quadrature demodulator
5
, the A/D converter
6
converts the analog baseband signal into a digital baseband signal.
The PLL circuit
7
is responsive to a reference clock signal generated by the TCXO
8
and produces the first local signal
16
1
to be supplied to the down converter
3
and the second local signal
16
2
to be supplied to the quadrature demodulator
5
. The TCXO
8
produces the reference clock signal having an oscillation frequency controlled by a control voltage produced by the accumulator
9
.
The delay profile/search circuit
12
is supplied with the digital baseband signal from the A/D converter
6
and produces profile data and a frame timing correction amount (&Dgr;t
1
). The profile data and the frame timing correction amount (&Dgr;t
1
) produced by the delay profile/search circuit
12
are shown in FIG.
2
. The profile data represents a profile of data including in the digital baseband signal. It is noted here that the frame timing correction amount (&Dgr;t
1
) is a discrete value because it is derived from a sampling rate of the A/D converter
6
.
The timing generating circuit
54
produces an ideal frame timing with reference to the reference clock signal from the TCXO
8
and adds to the ideal frame timing the frame timing correction amount (&Dgr;t
1
) produced by the delay profile/search circuit
12
to produce a frame timing signal
101
representative of the result of addition.
The demodulating circuit
10
comprises a RAKE receiver including a plurality of finger receivers and demodulates, with reference to the frame timing signal
101
, the digital baseband signal produced by the A/D converter
6
.
With reference to the frame timing signal
101
, the frequency offset estimating circuit
51
calculates the frequency error contained in the digital baseband signal from the A/D converter
6
. When the frequency error thus calculated becomes equal to or smaller than a predetermined value, the frequency offset estimating circuit
51
judges that the AFC operation is put in a locked state. When the frequency error becomes greater than the predetermined value, the frequency offset estimating circuit
51
judges that the AFC operation is put in an unlocked state. The frequency offset estimating circuit
51
informs the result of judgment to the CPU
53
by the use of a lock/unlock signal
106
.
Referring to
FIG. 3
, description will be made of calculation of the frequency error in the frequency offset estimating circuit
51
. The frequency error is calculated by the use of a symbol, such as a pilot symbol, having a symbol pattern which is preliminarily known on a receiver side. In
FIG. 3
, ideal symbol points
30
through
33
show symbols “00”, “01”, “10”, and “11” on an IQ plane in case where no frequency error is contained, respectively.
By way of example, consideration will be made about a signal modulated at 16 ksps by QPSK modulation. It is assumed that a pilot symbol at a particular timing has a symbol pattern “00” and that demodulation is carried out at a symbol point
20
obtained by rotation of &Dgr;&thgr;=10° on the IQ plane as illustrated in FIG.
3
. In this event, the frequency error is calculated by:
16k×10°/360°=44 Hz.
Therefore, by feeding back the frequency error through the accumulator
9
to the TCXO
8
, the AFC operation is put in the locked state, i.e., &Dgr;&thgr;÷0°. Then, the frequency offset estimating circuit
51
produces a lock/unlock signal
106
representative of the locked state and delivers the lock/unlock signal
106
to the CPU
53
.
Supplied with the lock/unlock signal
106
, the CPU
53
knows the current state of the AFC operation.
The accumulator
9
produces a control voltage and adds to a current value of the control voltage the frequency error calculated by the frequency offset estimating circuit
51
.
Referring to
FIGS. 1 through 3
, the operation of the conventional AFC circuit mentioned above will be described.
The reception signal received through the antenna
1
is amplified by the low-noise amplifier
2
and then converted by the down converter
3
into the IF signal by the use of the first local signal
16
, produced by the PLL circuit
7
. The IF signal is supplied to the AGC amplifier
4
to be gain-controlled so that the A/D converter
6
has a constant input level. The gain-controlled IF signal is supplied to the quadrature demodulator
5
to be quadrature-demodulated into the analog baseband signal by the use of the second local signal
162
produced by the PLL circuit
7
. The analog baseband signal is supplied to the A/D converter
6
to b

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