Automatic floorplan operation apparatus

Details Automatic floorplan operation apparatus Automatic floorplan operation apparatus

1990-05-15

1993-03-02

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

051915421

ABSTRACT:
Disclosed is an automatic floorplan operation apparatus for automatically performing a layout of cells onto a plurality of arrangeable areas which are optionally permitted to be overlapped on a chip. This apparatus evaluates degrees of cell densities in the respective arrangeable areas based on cell distributions therein by an objective function. When the evaluation is insufficient, an area definition correction unit also provided in the apparatus corrects the cell densities in accordance with FDM so that the cell densities in the overlapped and the independent areas are made uniform. This correction is carried out by a shift routine and a transformation routine, and is automatically repeated until the most suitable floorplan can be obtained.

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N. Quinn, Jr. et al, "A Forced Directed Component Placement Procedure for Printed Circuit Boards", IEEE Transactions on Circuits and Systems, vol. CAS-26, No. 6, Jun., 1979, pp. 377-388.
K. Nomura, et al, "An Efficient Block Placement Method for VLSI Design with Aspect-Ratio Modification Process", Dept. of Electrical and Electronic Engineering, Tokyo Institute of Tech., CAS87-236, pp. 13-18.
H. Onodera, et al, "A Block Placement Procedure Using a Force Model", Kyoto University, CAS-86-194, pp. 47-54.

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