Automatic fault recovery system for a multiple processor telecom

Details Automatic fault recovery system for a multiple processor telecom Automatic fault recovery system for a multiple processor telecom

1980-11-19

1983-02-01

Brown, Thomas W.

Excavating

371 9, 371 10, G06F 1120, H04M 308

Patent

active

043717543

ABSTRACT:
An automatic fault recovery system for a multiple processor control complex of a telecommunications switching system is disclosed. The fault recovery system has a hierarchical structure which deals with the occurrence of soft faults and localizes insofar as possible the effect of errors, with the goal of minimizing disruption of calls through the switching system. Included in the steps taken by the recovery system are rewriting memory locations in active memory units from standby memory units, switching between active and standby copies of memory units, bus units and central processor units, and instituting progressively more pervasive initializations of all the processors in the control complex. The recovery system includes an arrangement employing a memory block parity check for fast initialization. A time shared error detection and correction activity assures that standby copies of memory units are in condition to become active when required.

REFERENCES:
patent: 3409877 (1968-11-01), Alterman et al.
patent: 4256926 (1981-03-01), Pitroda et al.
"Fault-Tolerant Design of Local ESS Processors", W. N. Toy, Proceedings of the IEEE, vol. 66, No. 10, (Oct. 1978), pp. 1126-1145.
"System Recovery in the 2B Processor", Argoe and Wilber, GTE Automatic Electric Journal, Jul., 1979, pp. 141-148.
"Stored Program Multiregister", Mucientes et al., Electrical Communication, vol. 54, No. 4, 1979, pp. 271-280.
"A New System Handles Cross-Connections", J. R. Colton, Telephony, Dec. 8, 1980, pp. 74-82.
"The DMS-100 Distributed Control System, Fault Tolerance, Digital-Style", Bourne et al., Telesis (Bell-Northern Research, Canada), vol. 7, No. Four, 1980, pp. 6-12.

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