Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2000-08-17
2004-06-22
Corrielus, Jean B. (Department: 2631)
Pulse or digital communications
Equalizers
Automatic
C375S262000, C375S341000, C714S795000
Reexamination Certificate
active
06754263
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic equalizer that compensates a received signal that has been subject to distortion due to intersymbol interference, and in particular, relates to a technology for constraining the survivor paths based on the regularity of the code.
2. Description of the Related Art
Conventionally, a received signal has distortions due to the condition of its transmission channel. One method of compensating this distortion is using an automatic equalizer at the receiver. Here, a conventional automatic equalizer is explained referring to FIG.
8
.
FIG. 8
is a structural drawing of a conventional automatic equalizer.
In
FIG. 8
, reference numeral
501
is an estimation receiving circuit that generates k
M
estimated received signals by convolutionally processing k
M
series of candidate signals S
scan
that are a combination of transmitted code having an M chip length (where M is a natural number) and k levels (where k is a natural number) and the impulse response h of a transmission channel having length M, and outputs these generated k
M
estimated received signals S
er
. These k
M
estimated received signals S
er
are the signals that are estimated to be the received signals S
r
.
Reference numeral
502
is a subtracter that generates k
M
estimated error signals S
err
by subtracting the k
M
estimated received signals S
er
, from the received signal S
r
, and outputting these generated k
M
estimated error signals S
err
.
Reference numeral
503
is a Viterbi logic circuit that is structured from the path metric calculating circuit
504
and the survivor path selection circuit
505
, described below.
Reference numeral
504
is a path metric calculating circuit that inputs the k
M
estimated error signals S
err
and the k
M−1
survivor path metric signals S
pmsv
corresponding to each state of a trellis diagram, squares the absolute value of the k
M
estimated error signals S
err
corresponding respectively to the k
M−1
survivor path metric signals S
pmsv
to generate k
M
path metric signals S
pm
, and outputs these generated k
M
path metric signals S
pm
.
Reference numeral
505
is a survivor path selection circuit that inputs the k
M
path metric signals S
pm
, determines the smallest among the k
M
path metric signals S
pm
for each k
M−1
states, outputs these as k
M−1
survivor path metric signals S
pmsv
, and at the same time, among the k
M
series of candidate signals S
scan
, outputs as the decision output signals S
d
a portion of the series of candidate signals S
scan
corresponding to the smallest among the k
M−1
survivor path metric signals S
pmsv
. That is, the survivor path selection circuit
505
carries out the code decision of the received signals.
Reference numeral
506
is an error correction circuit that generates an error correction decision output signal S
ed
by correcting the decision output signal S
d
by the regularity of the code, and outputs this generated error correction decision output signal S
ed
.
However, the conventional automatic equalizer as described above carries out error correction using the error correction circuit
502
after code the decision, and thus in the case that an error in the code decision is propagated, the error correction effect by the error correction circuit
502
is diminished.
Therefore, in consideration of this problem, it is an object of the present invention to provide a technology that can resolve the above-described problem, and improve the error correction effect even in the case that an error in the code decision in the automatic equalizer is propagated.
SUMMARY OF THE INVENTION
The above described problems are resolved by an automatic equalizer characterized in comprising a received signal estimation circuit that inputs a k
M
series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number) and a transmission channel impulse response having a length M, and estimates a received signal by respectively carrying out convolutional processing on the k
M
series of candidate signals and the transmission channel impulse response having length M; a subtracter that inputs the received signal and the k
M
estimated received signals, generates k
M
estimated error signals by subtracting each of the k
M
estimated received signals from the received signal, and outputting the generated k
M
estimated error signals; a constraint condition selection circuit that inputs the received signal, generates a constraint condition selection signal that represents the regularity of the code of the received signal, and outputs this generated constraint condition selection signal; a constraint condition generation circuit that inputs the k
M
series of candidate signals and the constraint condition selection signal, determines the constraint condition for each of k
M−1
states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents and the k
M
series of candidate signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k
M
estimated error signals and the constraint condition signal, generates decision output signals based on the k
M
estimated error signals and the constraint condition signal, and outputs the generated decision output signals.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimated circuit that inputs a k
M
series of candidate signals that are combinations of a transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number) and a transmission channel impulse response having a length M, and estimates a received signal by respectively carrying out convolutional processing on the k
M
series of candidate signals and the transmission channel impulse response having length M; a subtracter that inputs the received signal and the k
M
estimated received signals, generates k
M
estimated error signals by subtracting each of the k
M
estimated received signals from the received signal, and outputting the generated k
M
estimated error signals; a constraint condition selection circuit that inputs decision output signals, generates constraint selection signal that represents the regularity of the code of the received signals, and outputs the generated constraint condition selection signal; a constraint condition generation circuit that inputs the k
M
series of candidate signals and the constraint condition selection signal, determines the constraint condition for each of k
M−1
states of a trellis diagram based on the regularity of the code that the constraint condition selection signal represents and the k
M
series of candidate signals, and outputs the constraint condition signal that represents the results of this decision, and a Viterbi calculation circuit that inputs the k
M
estimated error signals and the constraint condition signal, generates decision output signals based on the k
M
estimated error signals and the constraint condition signal, and outputs the generated decision output signals.
In addition, the above-described problems are resolved by an automatic equalizer characterized in comprising a received signal estimated circuit that inputs a k
M
series of candidate signals that are combinations of transmitted code having an M chip length (where M is a natural number) and k levels (where K is a natural number), k
M−1
hypothetical output signals having an N chip length (where N is a natural number), and a transmission impulse response having a length (M+N), and estimates a received signal by carrying out convolutional processing of the combination of the k
M
series of candidate signals and the k
M−1
hypothetical output signals respectively corresponding to the k
M
series of candidate sign
Corrielus Jean B.
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
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