Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1998-05-20
2001-09-25
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C375S233000, C375S232000, C369S047360, C369S059160
Reexamination Certificate
active
06295316
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an automatic equalization system for suppressing errors in a transmitted digital information signal. Also, this invention relates to a noise reduction circuit. Furthermore, this invention relates to a phase lock control circuit.
2. Description of the Related Art
It is known to transmit digital video and audio information signals via limited frequency bands. Also, it is known to reproduce digital video and audio information signals from recording mediums. The rate of errors in such a digital information signal tends to be adversely affected by noise. In addition, the rate of errors depends on the characteristic of a transmission path, the type of a recording medium, or the type of transmission.
There are prior-art automatic equalization systems of various types which operate to suppress errors in transmitted digital information signals. The prior-art automatic equalization systems implement level control, bit synchronization control, and waveform equalization. The level control adjusts the maximum level of signal samples at a given level to enable accurate detection of values represented by a transmitted digital information signal. The bit synchronization control adjusts a sampling clock signal into timing agreement with moments at which data bits are present. The waveform equalization compensates for deteriorations in high frequency components and low frequency components of a transmitted digital information signal, and also for inter-symbol interferences.
Generally, calibration and adjustment of portions of the prior-art automatic equalization systems are relatively complicated.
SUMMARY OF THE INVENTION
It is a first object of this invention to provide an improved automatic equalization system.
It is a second object of this invention to provide an improved noise reduction circuit.
It is a third object of this invention to provide an improved phase lock control circuit.
A first aspect of this invention provides an automatic equalization system comprising an analog-to-digital converter for periodically sampling an analog signal representative of digital information in response to a sampling clock signal, and for converting every sample of the analog signal into a corresponding digital sample to convert the analog signal into a corresponding digital signal; first means for detecting a phase error of the sampling clock signal in response to a correlation between samples of the digital signal generated by the analog-to-digital converter; second means for controlling a frequency of the sampling clock signal in response to the phase error detected by the first means; a variable filter for subjecting the digital signal generated by the analog-to-digital converter to a variable filtering process to convert the digital signal generated by the analog-to-digital converter into a filtering-resultant signal, the filtering process corresponding to a waveform equalization process; third means for detecting an amplitude error of the digital signal generated by the analog-to-digital converter in response to a correlation between samples of the filtering-resultant signal generated by the variable filter; and fourth means for controlling the filtering process implemented by the variable filter in response to the amplitude error detected by the third means; wherein the analog-to-digital converter, the first means, and the second means compose a phase locked loop while the variable filter, the third means, and the fourth means compose an amplitude error correcting loop separate from the phase locked loop.
A second aspect of this invention is based on the first aspect thereof, and provides an automatic equalization system wherein the first means comprises means for detecting the phase error in response to three successive samples of the digital signal generated by the analog-to-digital converter.
A third aspect of this invention is based on the first aspect thereof, and provides an automatic equalization system wherein the phase error of the sampling clock signal which is detected by the first means is defined relative to the analog signal.
A fourth aspect of this invention is based on the first aspect thereof, and provides an automatic equalization system wherein the first means comprises means for comparing a level of every sample of the digital signal generated by the analog-to-digital converter with a reference level, means for adaptively changing the reference level in response to the digital signal generated by the analog-to-digital converter, and means for detecting the phase error in response to a result of the level comparison.
A fifth aspect of this invention provides a noise reduction circuit comprising first means for deciding a level of every sample of an input signal representative of digital information in response to a maximum likelihood related to the input signal; second means for generating an ideal signal in response to the level decided by the first means; third means for calculating a difference between the input signal and the ideal signal generated by the second means; fourth means for generating a corrective signal in response to the difference calculated by the third means; and fifth means for correcting the input signal in response to the corrective signal generated by the fourth means.
A sixth aspect of this invention provides a noise reduction circuit comprising first means for deciding a level of every sample of an input signal representative of digital information in response to a maximum likelihood related to the input signal, and for generating a level decision signal representing the decided level; a first memory for storing successive samples of the level decision signal generated by the first means; a second memory for storing successive samples of the input signal, wherein the signal samples stored in the second memory correspond to the signal samples stored in the first memory respectively; second means for comparing a first pattern represented by a given number of last successive samples of the level decision signal with second patterns represented by the signal samples in the first memory to detect, from among the second patterns, a past pattern corresponding to the first pattern, and for generating an address signal in response to a position of the detected past pattern; third means for selecting a signal sample from among the signal samples in the second memory in response to the address signal generated by the second means; fourth means for calculating a difference between the signal sample selected by the third means and a corresponding sample of the input signal; fifth means for generating a corrective signal in response to the difference calculated by the fourth means; and sixth means for correcting the input signal into a correction-resultant signal in response to the corrective signal generated by the fifth means.
A seventh aspect of this invention is based on the sixth aspect thereof, and provides a noise reduction circuit further comprising seventh means for writing a present sample of the correction-resultant signal over a corresponding signal sample in the second memory.
An eighth aspect of this invention provides a phase lock control circuit comprising an analog-to-digital converter for periodically sampling an analog signal representative of digital information in response to a sampling clock signal, and for converting every sample of the analog signal into a corresponding digital sample to convert the analog signal into a corresponding digital signal; first means for detecting a phase error between the sampling clock signal and the analog signal in response to a maximum likelihood related to the analog signal and also in response to a correlation between samples of the digital signal generated by the analog-to-digital converter; and second means for controlling a frequency of the sampling clock signal in response to the phase error detected by the first means.
A ninth aspect of this invention is based on the eighth aspect thereof, and provides a phase lock control
Kiyofuji Takashi
Tonami Junichiro
Chin Stephen
Liu Shuwang
Victor Company of Japan Ltd.
Woo Louis
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