Automatic differential absolute time delay equalizer

Pulse or digital communications – Equalizers – Automatic

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375 229, 375257, 375347, 455303, 4552761, 333 28R, 333142, H03H 730, H03H 500, H04B 110, H04B 106

Patent

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058286993

ABSTRACT:
A circuit and method for automatically reducing an electrical path length difference between two electromagnetic signal paths. A counter converts the electrical path length difference to a multi-bit digital signal, and each bit in the signal operates a different one of plural switches which selectively inserts a time delay into one of the two electromagnetic signal paths to reduce the electrical path length difference. A comparator determines whether the electrical path length difference exceeds a threshold. The rectified AC component of a phase detector output is fed to the comparator which activates the counter when the threshold is exceeded. The counter drives the switched time delays in a sweeping fashion until the detected error falls below the threshold, whereupon the sweeping action is terminated.

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patent: 5663735 (1997-09-01), Eshenbach

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