Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Target device
Reexamination Certificate
2005-02-08
2005-02-08
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Target device
C703S001000, C703S022000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06853970
ABSTRACT:
A method for the automatic design of processor datapaths operates on an abstract input specification of desired processor operations and their instruction level parallelism and synthesizes a datapath design in machine readable form. A datapath synthesizer automatically designs and synthesizes the processor datapath including the number and types of functional units, the number of read/write ports of the various register files, and the exact connectivity between the register files and the functional units. The heuristics used in the implementation maximize resource sharing and minimize the overall cost in by customizing and sharing functional units and minimizing the number of read/write ports on the register files subject to the specified ILP among operations.
REFERENCES:
patent: 5502645 (1996-03-01), Guerra et al.
patent: 5513123 (1996-04-01), Dey et al.
patent: 5530884 (1996-06-01), Sprague et al.
patent: 5831991 (1998-11-01), Miller et al.
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6351142 (2002-02-01), Abbott
Li et al, “An Algorithm to Determine Mutually Exclusive Operations In Behavioral Descriptions,” IEEE Proceedings of Design, Automation and Test in Europe, pp. 457-463 (Feb. 1998).*
Ravikumar et al, “A Graph-Theoretic Approach for Register File Based Synthesis,” IEEE Proceedings of the 10thInternational Conference on VLSI Design, pp. 118-123 (Jan. 1997).*
Zobel, “Program Structure as Basis for Parallelizing Global Register Allocation,” IEEE Proceedings of the 1992 International Conference on Computer Languages, pp. 262-271 (Apr. 1992).*
Chen, “Allocation of Multiport Memory With Ports of Different Type in Register Transfer Synthesis,” 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 418-421 (Oct. 1991).*
Rainer Leupers, Peter Marwedel, “Retargetable Generation of Code Selectors from HDL Processor Models,” IEEE, 1997, pp. 140-144.
George Hadjiyiannis, Silvina Hanono, Srivinas Devadas, “ISDL: An Instruction Set Description Language for Retargetability,” ACM, 1997, pp. 299-302.
Gyllenhaal et al., “HMDES Version 2.0 Specification,” Helwett Packard Laboratories Technical Report IMPACT-96-3.
Hadjiyiannis et al., “A Methodology for Accurate Performance Evaluation in Architecture Exploration.”
Hoogerbrugge et al., “Automatic Synthesis of Transport Triggered Processors.”
Corporaal et al., “MOVE: A Framework for High-Performance Processor Design,” ACM, 1991, pp. 692-701.
Corporaal et al., “Cosynthesis with the MOVE Framework.”
Lanneer et al, “Chapter 5—Chess: Retargetable Code Generation for Embedded DSP Processors,” Code Generation for Embedded Processors, Kluwer Academic Publications, pp. 85-102.
Fauth, “Chapter 8—Beyond Tool-Specific Machine Descriptions,” Code Generation for Embedded Processors, Kluwer Academic Publications, pp. 138-152.
G. J. Chaitin, “Register Allocation & Spilling Via Graph Coloring,” ACM, 1982, pp. 98-105.
Fisher et al., “Custom-Fit Processors: Letting Applications Define Architectures,” 29thAnnual Conference IEEE/ACM International Symposium on Microarchitecture, Dec. 2-4, 1996, Paris, France, pp. 324-336.
Aditya et al., “Elcor's Machine Description System: Version 3.0” HPL-98-128, Oct. 1998, pp. 1-75.
Rau et al., “Machine-Description Driven Compilers for EPIC Processors,” HP Laboratories Technical Report, HPL-98-40, Sep. 1998, pp. 1-82.
Kathail et al., “HPL PlayDoh Architecture Specification: Version 1.0,” HP Laboratories Technical Report, HPL-93-80, Feb. 1994, pp. 1-48.
Gupta Shail Aditya
Rau B. Ramakrishna
LandOfFree
Automatic design of processor datapaths does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic design of processor datapaths, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic design of processor datapaths will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3472810