Automatic delay adjustment for static timing analysis using cloc

Details Automatic delay adjustment for static timing analysis using cloc Automatic delay adjustment for static timing analysis using cloc

1995-09-18

1998-06-23

Heckler, Thomas M.

G06F 108

Patent

active

057713758

ABSTRACT:
An apparatus and method are disclosed that perform static timing analysis on a logic circuit. The logic circuit is unique in that it includes a path topology having a mixture of full cycle and half cycle timing paths. The apparatus and method first perform a data event identification event on the logic circuit and use this event to define a set of clock-to-data-phase transformation rules for defining in all latch instances of the circuit, how each data phase is generated and from what clock edge each data phase is created. Next, the system then performs a test edge selection and then performs a clock adjustment based on the transformation rules and the test edge selection. In performing the test edge selection, the system selects a correct time leading or time trailing edge based on which edge level of the clock is the level against which an arriving data signal to be tested. The clock adjustment is further performed by examining a test edge associated with the data phase associated with the arriving data signal to be tested, selecting a full cycle adjustment, which is the same as the edge launched by the data signal, and then performing a half cycle adjustment if the test edge is opposite the edge launched by the data signal.

REFERENCES:
patent: 4443883 (1984-04-01), Berger
patent: 4807109 (1989-02-01), Farrell
patent: 4851995 (1989-07-01), Hsu et al.
patent: 4870562 (1989-09-01), Kimoto et al.
patent: 4949249 (1990-08-01), Lefsky et al.
patent: 5210700 (1993-05-01), Tom
patent: 5210858 (1993-05-01), Horst
patent: 5222230 (1993-06-01), Gill et al.
patent: 5274796 (1993-12-01), Conner
patent: 5297276 (1994-03-01), Millar et al.
patent: 5303365 (1994-04-01), Getzlaff et al.
patent: 5305451 (1994-04-01), Chao et al.
patent: 5347559 (1994-09-01), Hawkins et al.
patent: 5388249 (1995-02-01), Hotta et al.
patent: 5544071 (1996-08-01), Keren et al.
patent: 5579510 (1996-11-01), Wang et al.

Affiliated with

Also associated with

Rating

Automatic delay adjustment for static timing analysis using cloc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic delay adjustment for static timing analysis using cloc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic delay adjustment for static timing analysis using cloc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1400721