Automatic code generation for integrated circuit design

Details Automatic code generation for integrated circuit design Automatic code generation for integrated circuit design

2006-02-07

2006-02-07

Chaki, Kakali (Department: 2193)

Data processing: software development, installation, and managem

Software program development tool

Code generation

C717S104000, C717S120000, C703S014000, C716S030000

Reexamination Certificate

active

06996799

ABSTRACT:
An integrated circuit is designed by interconnecting pre-designed data-driven cores (intellectual property, functional blocks). Hardware description language (e.g. Verilog or VHDL) and software language (e.g. C or C++) code for interconnecting the cores is automatically generated by software tools from a central circuit specification. The central specification recites pre-designed hardware cores (intellectual property) and the interconnections between the cores. HDL and software language test benches, and timing constraints are also automatically generated from the central specification. The automatic generation of code simplifies the interconnection of pre-existing cores for the design of complex integrated circuits.

REFERENCES:
patent: 5377122 (1994-12-01), Werner et al.
patent: 5408667 (1995-04-01), Brodie et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5678052 (1997-10-01), Brisson
patent: 5734572 (1998-03-01), Guignet
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5892682 (1999-04-01), Hasley et al.
patent: 5910897 (1999-06-01), Dangelo et al.
patent: 5995736 (1999-11-01), Aleksic et al.
patent: 6006028 (1999-12-01), Aharon et al.
patent: 6145073 (2000-11-01), Cismas
patent: 6151568 (2000-11-01), Allen et al.
patent: 6199031 (2001-03-01), Challier et al.
patent: 6205407 (2001-03-01), Testa et al.
patent: 6212566 (2001-04-01), Vanhoof et al.
patent: 6226780 (2001-05-01), Bahra et al.
patent: 6233540 (2001-05-01), Schaumont et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6347388 (2002-02-01), Hollander
patent: 6421808 (2002-07-01), McGeer et al.
patent: 6446243 (2002-09-01), Huang et al.
patent: 2003/0018738 (2003-01-01), Boylan et al.
Zainalabedin Navabi; “VHDL: Analysis and Modeling of Digital Systems”; McGraw-Hill, 2nd Edition; 1998.
Madisetti et al.; “Interface Design for Core-Based Systems”; IEEE Design and Test of Computers; 1997; pp. 42-51.
Rincon et al.; “Core Design and System-on-a-Chip Integration”; IEEE Design and Test of Computers; 1997; pp. 26-35.
Gupta et al.; “Introducing Core-Based System Design”; IEEE Design and T st of Computers; 1997; pp. 15-25.
Hutchins et al, “Automating IP Core Design, Configuration, and Verification,” Gigapixel Corp. paper; paper footer contains marking “SNUG '99.”

Affiliated with

Also associated with

Rating

Automatic code generation for integrated circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic code generation for integrated circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic code generation for integrated circuit design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3705402