Pulse or digital communications – Synchronizers
Reexamination Certificate
2000-09-21
2004-09-28
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Synchronizers
C375S285000
Reexamination Certificate
active
06798856
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to, for example, in an information processing system comprising a plurality of components between which interchange of data takes placer an automatic clock tuning method, an automatic clock tuning control system and an apparatus having an automatic clock tuning function, each of which accomplishes automatic tuning of a phase of a clock to transmission latch or receive latch in each of the components so that the transfer of data between these components is achievable within a predetermined number of clock cycles.
2) Description of the Related Art
In general, an information processing system is constructed as a cluster in which, for example, a plurality of components (CPU, and others) are connected to a single control unit.
In addition, in such an information processing system, the transfer of data among components is performed surely within a predetermined number of clock cycles (for example, one clock cycle) through the use of a plurality of types of system clocks different in phase from each other, thereby enhancing the efficiency of the data transfer.
Concretely, allowing for a data transfer delay corresponding to a length of a data bus between the components, a system clock [E (Early) clock] advancing somewhat in phase with respect to a normal system clock [N (Normal) clock] is supplied to a transmission latch for sending data to a data bus in a component on the transmission side, while a system clock [L (late) clock] retarding somewhat in phase relative to the normal system clock is given to a receive latch for receiving data from a data bus in a component on the receive side.
Therefore, data from the transmission side to the receive side is forwarded through a transmission latch to a data bus on the somewhat early side (somewhat early), while the receive latch latches data from a data bus on the somewhat late side (somewhat latish).
Such adjustment of the phase of the system clock to the transmission buffer or the receive buffer enables reliable data transfer among the components within a predetermined number of clock cycles without suffering the effects of a data transfer delay stemming from the length of the data bus. Incidentally, needless to say, such system clock phase adjustment will be made in a manner of avoiding reflecting on the data transfer in each of the components.
Furthermore, in general, prior to the information processing system being put on the market, such system clock relative phase adjustment or absolute phase adjustment is made manually through the use of a tester dedicated to clock tuning to optimize (accomplish the clock tuning) the relationship in phase among the aforesaid plurality of types of system clocks.
Meanwhile, with the enlargement in information processing system scale, extension (additional installation) or replacement in units of components in the information processing system constitutes an effective and important means for improvement of performance or maintenance of the information processing system. If a portion undergoing such extension or replacement forms a portion of a central processing unit (CPU), that extension/replacement requires quick work and, particularly, high reliability. Therefore, there is a need to facilitate the extension/replacement on the user side of the information processing system.
For realizing the facilitation of the extension/replacement, regardless of the function of a device to be additionally installed or replaced (particularly, even if a device to be replaced has the same function as that of the device before the replacement or has a newly added function), there is a need to optimize the relationship in phase among a plurality of system clocks so that the data transfer between the components is surely achievable within a predetermined number of clock cycles and a trouble to the data transfer in each of the components is a voidable.
For this reason, a method called “operating margin guarantee” has been put to use. That is, in performing the manual clock tuning through the use of the clock tuning dedicated tester as mentioned above, this is for securing a larger range in which the relationship in phase among the aforesaid plurality of system clocks is optimal, thereby absorbing the physical differences between the devices to be additionally installed or replaced or the differences resulting from the functions thereof. Thus, in addition to the operational margin needed for the real operation, the foregoing operating margin includes an operating margin which can accept the aforesaid extension/replacement work.
However, as stated above, the current clock tuning has been conducted manually through the use of the clock tuning dedicated tester prior to the information processing system being put on the market, which has required a great labor penalty.
In addition, as stated above, since, in addition to the guarantee on the operating margin needed for the real operation, the clock tuning has been conducted while providing guarantee of an operating margin taking into consideration devices to be additionally installed or replaced after the installation of the information processing system, a considerably larger operating margin than needed actually becomes necessary. For this reason, an increase in system scale or an enlargement in system operating frequency, the ratio of the operating margin to the operating frequency increases, which makes it difficult to secure the operating margin. Contrary to this, the enlargement of such an operating margin securing range sometimes imposes the limitation on the system performance, such as reducing operating frequency.
Meanwhile, if, whenever an alteration or change of system configuration takes place, the relationship in phase among a plurality of system clocks can be optimized according to the device alteration, then it is possible to eliminate the need for wasteful guarantee of an operating margin for the device to be additionally installed or replaced, which allows an operating frequency corresponding to a system performance to be set, thus eliminating the limitation on the system performance.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been developed with a view to solving the above-mentioned problems, and it is therefore an object of the invention to provide an automatic clock tuning method, an automatic clock tuning control system and an apparatus having an automatic clock tuning function, which are capable of automatically and quickly optimizing the relationship in phase among clocks at installation of a system or at extension thereof for cutting the labor needed for the clock tuning, and further of securing only an operating margin needed for the real operation without providing guarantee on a useless operating margin, thus exhibiting the maximum of system performance.
For this purpose, in accordance with the present invention, there is provided an automatic clock tuning method of automatically tuning a phase of a clock to a transmission latch for sending data to a data bus in a transmission side component and a phase of a clock to a receive latch for receiving data from a data bus in a receive side component, comprising an operation of adjusting the phase of the clock to the transmission latch in the transmission side component, an operation of generating a data pattern for a clock phase check in the transmission side component, an operation of switching a circuit in the transmission side component to send the data pattern through the transmission latch to the data bus, an operation of adjusting the phase of the clock to the receive latch in the receive side component, an operation of verifying, on the basis of the data pattern received by the receive latch from the transmission side component, as to whether or not the data transfer from the transmission side component to the receive side component is accomplished within a predetermined number of clock cycles, and an operation of adjusting the phase of the clock to the transmission
Yamaguchi Kazue
Yoshimura Katsuyoshi
Arent & Fox PLLC
Fujitsu Limited
Ghebretinsae Temesghen
Kumar Pankaj
LandOfFree
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