Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
2009-10-16
2011-12-27
Grey, Christopher (Department: 2474)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S516000, C370S517000, C370S537000, C375S362000, C375S371000, C375S375000, C375S355000, C327S144000, C327S161000
Reexamination Certificate
active
08085817
ABSTRACT:
A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.
REFERENCES:
patent: 5095233 (1992-03-01), Ashby et al.
patent: 6064244 (2000-05-01), Wakayama et al.
patent: 6847241 (2005-01-01), Nguyen et al.
patent: 7123058 (2006-10-01), Kim et al.
patent: 7190201 (2007-03-01), Haerle et al.
patent: 7580496 (2009-08-01), Marbot et al.
patent: 7627003 (2009-12-01), Fouts et al.
patent: 2002/0047742 (2002-04-01), Setagawa
patent: 2003/0132790 (2003-07-01), Amick et al.
patent: 2004/0189359 (2004-09-01), Shah et al.
Fouts Douglas Jai
Luke Brian Lee
Grey Christopher
Lincoln Donald E.
Norris Lisa A.
The United States of America as represented by the Secretary of
LandOfFree
Automatic clock synchronization and distribution circuit for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic clock synchronization and distribution circuit for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic clock synchronization and distribution circuit for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4263408