Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
2005-09-30
2009-12-01
Moe, Aung S (Department: 2416)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S516000, C375S362000, C375S371000, C375S375000, C375S355000, C327S141000, C327S144000, C327S158000, C327S161000
Reexamination Certificate
active
07627003
ABSTRACT:
A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.
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Fouts Douglas Jai
Luke Brian Lee
Grey Christopher P
Lincoln Donald E.
Moe Aung S
Norris Lisa A.
The United States of America as represented by the Secretary of
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