Automatic clock switching

Details Automatic clock switching Automatic clock switching

1999-09-27

2001-02-27

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000

Reexamination Certificate

active

06194940

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to systems with multiple clock sources and, in particular, to switching between clock sources.
2. Description of the Related Art
Systems employing computer processors often provide multiple clock sources which can be used as a system clock to drive the processor, other components of the system, or the entire system. For example, various comparatively “fast” and “slow” clocks may be available. Fast clocks include the default external clock and a phase-locked loop (PLL) clock. The external clock may run at 100 MHz, for example, and is a crystal-based clock. The PLL clock may run at a multiple of this frequency, e.g. at 200 MHz.
Slow clocks include a ring oscillator and an internal “real-time” clock. The ring oscillator provides an inexact frequency, e.g. in the range of 20-100 kHz. An internal clock typically requires a crystal and may run at a fixed, exact frequency of 32 kHz, for example.
In many devices, it is desired to save power and thus the system utilizes slower clocks when possible to save power. For example, in a cordless or cell phone containing a microprocessor system, a real-time clock may be utilized when the phone is in “sleep” mode. Alternatively, if the real-time clock is not available because it is not desired to install a crystal, the ring oscillator may be used in sleep mode. The phone occasionally needs to wake up. This may happen in response to a periodic interrupt signal INT received from a timer circuit (the “wait-for-interrupt” mode), or in response to a wake up signal generated by the processor in response to the user turning on the phone.
When this occurs, a higher speed clock, such as the external clock, needs to be switched to. If the external clock is in use and the application running on the processor determines that even more speed is necessary, the system can switch the system clock from the external clock to the PLL clock.
When the system is using one of the faster clocks, it is sometimes desired to switch to one of the slow clocks, e.g. when the phone enters sleep mode or is turned off by the user. A network of switches or multiplexers (MUXes) under the control of select control signals are typically used to route the appropriate output clock signal from the selected clock source to the system or other component that is to use the selected clock signal.
In such systems having several clocks of differing frequencies, a way of switching between such sources is needed. Current techniques are unsatisfactory for a variety of reasons. The programmer of the application run by the processor (typically stored in a ROM in the system) must manually program a large and complex number of instructions to ensure that the switching is done properly. Moreover, because these instructions are executed by fetching them one at a time from memory, there can be undesirable delays in switching clock sources. In addition, if the processor is using a slow clock, it executes the instructions to switch to a faster clock at the slower clock rate, thus further delaying the clock switch.
Thus, in previous techniques, the programmer has to manually perform the switch by repeatedly executing instructions which write values to control registers within the clock switch circuitry. This can be complicated because different types of clock sources have their own way of controlling the switching process. For example, to switch from one clock source to a PLL clock, the programmer must program the following instructions to occur:
1. Turn on the PLL clock;
2. Wait for lock to occur (this step itself may require many instructions);
3. Switch to the PLL clock; and
4. Turn off the previous source.
A disadvantage of this technique is the large number of instructions that must be written by the programmer, and the delay that will be caused during the switch as these instructions are executed by the processor.
When running the processor with a slow clock (e.g., the real-time clock or a ring oscillator) in wait-for-interrupt mode, it is important for the clock switching circuitry to switch to the fast clock as quickly as possible. Current designs rely on the execution of an “interrupt” sequence of instructions similar to those listed above:
1. See the interrupt;
2. The processor branches to the interrupt code (sequence of instructions);
3. Switch to the faster clock (either PLL clock or external clock, for example).
Because the system is running on the slower clock for most of these instructions, the time to respond to an interrupt can be slower than desired.
SUMMARY
In the present invention, a clock switch controller has a clock status register which stores current clock data which identifies which of two or more clock signal sources is a current clock signal source currently in use as a system clock signal source. State machine logic of the controller automatically switches, in response to a clock switch signal, the system clock signal source from the current clock signal source to a new clock signal source of the two or more clock signal sources.


REFERENCES:
patent: 5136180 (1992-08-01), Caviasca
patent: 5845139 (1998-12-01), Fischer et al.
patent: 5929713 (1999-07-01), Kubo et al.
patent: 6084441 (2000-07-01), Kawai

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