Automatic clock signal phase adjustment in which a pattern inclu

Details Automatic clock signal phase adjustment in which a pattern inclu Automatic clock signal phase adjustment in which a pattern inclu

1997-02-14

1998-12-22

Hindi, Nabil

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

360 40, 360 46, 360 61, 360 65, G11B 509

Patent

active

058525254

ABSTRACT:
An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method. The automatic clock signal phase adjusting circuit comprises: a pattern detection circuit for detecting at least one of patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal; a level detection circuit for detecting the levels of the reproduced signal in effect when the pattern detection circuit detects 0's; a clock reproduction circuit for reproducing a clock signal from the reproduced signal; and a phase adjustment circuit for adjusting the phase of the clock signal reproduced by the clock reproduction circuit based on the output signal from the level detection circuit.

REFERENCES:
patent: 3864529 (1975-02-01), Tracey et al.
patent: 5615059 (1997-03-01), Seki et al.
patent: 5615060 (1997-03-01), Seki et al.

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