Automatic clock signal phase adjusting circuit utilizing level d

Details Automatic clock signal phase adjusting circuit utilizing level d Automatic clock signal phase adjusting circuit utilizing level d

1995-05-03

1997-03-25

Psitos, Aristotelis

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

360 46, 360 61, 360 65, G11B 2736, G11B 501

Patent

active

056150601

ABSTRACT:
An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method. The automatic clock signal phase adjusting circuit comprises: a pattern detection circuit for detecting at least one of patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal; a level detection circuit for detecting the levels of the reproduced signal in effect when the pattern detection circuit detects 0's; a clock reproduction circuit for reproducing a clock signal from the reproduced signal; and a phase adjustment circuit for adjusting the phase of the clock signal reproduced by the clock reproduction circuit based on the output signal from the level detection circuit.

REFERENCES:
patent: 4272845 (1981-06-01), Fiumani
patent: 5210712 (1993-05-01), Saito

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