Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-12-29
2001-12-04
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S047000
Reexamination Certificate
active
06326830
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to clocking systems. In particular, the present invention relates to computers with a multiple clock signal distribution network.
2. Description of the Related Art
Computer systems typically include clock generator sources that have multiple clock signal outputs with multiple frequencies. Although such clock generator sources are commercially available in the form of integrated circuit (IC) chips, computer systems (especially large computer systems such as servers) frequently need more clock signal outputs than the limited number provided by a single chip. They therefore use a multiple chip clock distribution network consisting of a plurality of “fanout” ICs that receive a single input clock signal and drive a plurality of clock output signals.
Regardless of the number of clock output signals, they must all arrive at their respective loads in phase within a small skew window from each other. A skew window on the order of a few hundred pico-seconds (ps) is difficult to achieve because the input to output propagation delays between different fanout ICs are usually several times larger than the targeted skew window.
A common solution to this problem incorporates commercially available programmable delay chips in the multiple chip clock distribution network. With step sizes down to 20 ps, these programmable delay chips allow the clock signals in a computer system to be de-skewed manually. Delay can be added to clocks coming from fanout ICs having shorter propagation delays to compensate for fanout ICs with longer propagation delays in the distribution network. But even with only a few programmable delay chips in the computer system the process of manually calibrating the clock signals by taking repeated skew measurements and then adjusting (usually via DIP switches) the programmable delays can be quite time consuming. Additionally, changes in temperature and voltage affect each fanout IC differently resulting in an unacceptable skew between the different fanout ICs even though a manual calibration has been successfully performed.
BRIEF SUMMARY
An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences.
REFERENCES:
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patent: 5548621 (1996-08-01), Brady et al.
patent: 5598156 (1997-01-01), Hush et al.
patent: 5963069 (1999-10-01), Jefferson et al.
patent: 6075832 (2000-06-01), Geannopoulos et al.
patent: 6173432 (2001-01-01), Harrison
Brady Gary
Moberly Jerry
Nevard Pete
Rees Roger R
Swider Christopher P.
Antonelli Terry Stout & Kraus LLP
Intel Corporation
Nu Ton My-Trang
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