Automatic calibration circuit for a continuous-time equalizer

Pulse or digital communications – Equalizers

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S230000, C375S231000, C375S232000, C375S233000, C333S018000, C333S02800T

Reexamination Certificate

active

07826522

ABSTRACT:
Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

REFERENCES:
patent: 6995627 (2006-02-01), Casper et al.
patent: 7003028 (2006-02-01), Bishop et al.
patent: 2004/0041652 (2004-03-01), Takahashi
patent: 2005/0185710 (2005-08-01), Gai et al.
patent: 2006/0019627 (2006-01-01), Talbot
Choi, et al., “A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method”, Mar. 2004, IEEE Journal of Solid State Circuits, vol. 39, p. 419-425.
United States Patent Application, pending, not yet published, U.S. Appl. No. 11/648,340, filed Dec. 28, 2006, to Taner Sumesaglam.
Hartman et al., “Continuous-Time Adaptive-Analog Coaxial Cable Equalizer in 0.5um CMOS”, Dept. of Electrical/Computer Engineering, Univ. of Toronto, 1999 IEEE, pp. 97-100.
Tam et al., “A Novel Mixed-Mode Adaptive Equalization System for High-Speed 2-Level Pam Signals”, IEEE Symp. on Circuits and Systems, May 2000, pp. 749-752.
Lee et al., “Low-Power Area-Efficient High-Speed I/O Circuit Techniques”, IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1591-1599.
Casper et al., “An Accurate and Effifcient Analysis Method for Multi-Gb/s Chip-to-chip Signaling Schemes”, 2002 Symp. on VSLI Circuits Digest of Technical Papers, pp. 54-57.
Zhang et al., “A BiCMOS 10Gb/s Adaptive Cable Equalizer”, Dept. of ECE, Univ. of California Irvine, 2003 IEEE, pp. 49-52.
Hanumolu et al., “Analysis of PLL Clock Jitter in High-Speed Serial Links”, IEEE Trans. on Circuits and Systems II, Analog/Digital Signal Procs., vol. 50, No. 11, pp. 879-886.
Zerbe et al., “Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplance Transceiver Cell”, IEEE Jour of Solid-State Circuits, vol. 38, No. 12, pp. 2121-2130.
Hoyos et al., “Mixed-Signal Equalization Architectures for Printed Circuit Board Channels”, IEEE Trans on Circuits/Systems I, vol. 51, No. 2, pp. 264-274.
Choi et al., “A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer using Enhanced Low-Frequency Gain Control Method”, Jour of Soild-State Circuits, vol. 39, No. 3.
Balamurugan et al., “Receiver Adaption and System Characterizations of an 8Gbps Source-Synchronous I/O Link using On-Die Circuits in 0.13um CMOS”, 2004 Symposium on VLSI Circuits Digest of Technical Papers, pp. 356-359.
Lin et al., “A Digital Power Spectrum Estimation Method for the Adaption of High-Speed Equalizers”, IEEE Trans on Circuits and Systems I, vol. 51, No. 12, pp. 2436-2443.
Jaussi et al., “8-Gb/s Source-Synchronous I/O Link with Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew”, IEEE Jour of Solid-State Circuits, vol. 40, No. 1, pp. 80-88.
Sorna et al., “A 6.4 Gb/s CMOS SerDes Core with Feedfoward and Decision-Feedback Equalization”, 2005 IEEE International Solid-State Circuit Conference, pp. 62-63, & 585.
Gondi et al., “A 10 Gb/s CMOS Adaptive Equalizer for Backplane Applications”, 2005 IEEE International Solid-State Circuit Conference pp. 328-329, & 601.
Payne et al., “A 6.25-Gb/s Binary Transceiver in a 0.13um CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels”, IEEE Journal of Solid-State Circuits vol. 40, No. 12, pp. 2646-2657.
Jri Lee, “A 20-Gb/s Adaptive Equalizer in 0.13um CMOS Technology”, IEEE Journal of Solid-State Circuits, vol. 41, No. 9, pp. 2058-2066.
Hollis et al., “Mitigating ISI Through Self-Calibrating Continuous-Time Equalization”, IEEE Trans on Circuits and Systems I, vol. 53, No. 10, pp. 2234-2245.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Automatic calibration circuit for a continuous-time equalizer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic calibration circuit for a continuous-time equalizer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic calibration circuit for a continuous-time equalizer will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4248605

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.