Automatic cache flush with readable and writable cache tag memor

Details Automatic cache flush with readable and writable cache tag memor Automatic cache flush with readable and writable cache tag memor

1992-05-04

1994-02-15

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 36424341, 395400, G06F 1200, G06F 1300

Patent

active

052874818

ABSTRACT:
According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no "valid" bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.

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OPTi, Inc. HiD/386 AT Chipset High Integration Direct Mapped Cache AT 82C381/82C382D-25/33 Data Book (Nov. 1989).
Buchanan, "A Highly Integrated VLSI Chip Set For EISA System Design", Silicon Valley Personal Computer Design Conference Proceedings, Jul. 9-10, 1991, pp. 293-306.

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