Automatic cache bypass for instructions exhibiting poor cache hi

Details Automatic cache bypass for instructions exhibiting poor cache hi Automatic cache bypass for instructions exhibiting poor cache hi

1991-04-15

1997-04-29

Swann, Tod R.

395471, G06F 1212

Patent

active

056257937

ABSTRACT:
A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction's behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.

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Clark et al., "Adaptive Data Staging Mechanism in a Virtual Storage System", IBM Technical Disclosure Bulletin, vol. 17, No. 1, Jun. 1974, pp. 210-214.

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