Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-02-26
2011-11-15
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S111000, C716S112000, C716S130000, C716S137000, C716S139000
Reexamination Certificate
active
08060849
ABSTRACT:
Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance between pins and routing layer of the pins. A bus routing area is determined by the bounding box of first group of source pins and a second group of destination pins. Bus routing guidance is then generated by an automatically search engine in the bus routing area. The bus routing guidance models a bus as a skinny wire with large spacing, and it does not violate design rules. Real bus wires are generated based on the bus guidance. A bus is then automatically routed between a first group of source pins and a second group of destination pins based on the bus routing guidance.
REFERENCES:
patent: 5847968 (1998-12-01), Miura et al.
patent: 6253364 (2001-06-01), Tanaka et al.
patent: 6256769 (2001-07-01), Tamarkin et al.
patent: 7257797 (2007-08-01), Waller et al.
patent: 7793249 (2010-09-01), Wadland et al.
patent: 2004/0025132 (2004-02-01), Valine
patent: 2004/0250230 (2004-12-01), Itou et al.
patent: 2005/0229138 (2005-10-01), Kitamura et al.
patent: 2005/0235243 (2005-10-01), Hachiya et al.
PCT International Search Report and the Written Opinion of the International Searching Authority for International Application No. PCT/US2009/034899, Apr. 14, 2009 pp. 1-7.
Cadence Design Systems, Inc. “Virtuoso Chip Assembly Router Datasheet,” 2007, 4 pages.
Cadence Design Systems, Inc., “Virtuoso® Layout Editor User Guide,” Sep. 2003, 924 pages.
MicroSim Corporation, “MicroSim PCBoards Autorouter User's Guide,” Version 8.0, Jun. 1997, 135 pages.
Premkumar, “Accelerating Chip-Level Routing and Design,” Sep. 2005, 9 pages.
Premkumar, “Automated Custom Physical Design (ACPD) Flow in Cadence IC5.0.x for Mixed-Signal Designs,” downloaded from http://www.cdnusers.org/community/virtuoso/resources/tp—ACPDFlowforMSdesigns.pdf on May 25, 2010, 9 pages.
Gong MingFu
He Yanyan
Lin Gary
Nguyen Hung
Dinh Paul
Klarquist & Sparkman, LLP
Mentor Graphics Corporation
Nguyen Nha
LandOfFree
Automatic bus routing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic bus routing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic bus routing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4284691