Automatic baud rate detector

Details Automatic baud rate detector Automatic baud rate detector

1997-06-16

1999-11-09

Bocure, Tesfaldet

Pulse or digital communications

Miscellaneous

H04B 166

Patent

active

059828374

ABSTRACT:
An automatic baud rate detector circuit includes a serial input, a counter, a register, a comparator and a state machine circuit. The serial input receives a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and next subsequent second transition from the second logic state to the first logic state. A counter increments a sample count in response to a clock signal when a count enable signal supplied to the counter is active. A register coupled to the counter stores the sample count as a minimum count when a load control signal supplied to the counter is active. The comparator is coupled to the counter and the register and generates a compare signal which indicates whether the sample count is less than the minimum count. The state machine circuit is coupled to the serial input for receiving the serial data stream and supplies the count enable signal to the counter and the load enable signal to the register. The state machine circuit activates the count enable signal from the first transition to the second transition in the serial data stream and activates the load enable signal when the first compare signal indicates the sample count is less than the minimum count. After one or more cycles of the state machine circuit, the minimum count stored in the register can be used to calculate the baud rate of the serial data stream.

REFERENCES:
patent: 3775751 (1973-11-01), Anderson
patent: 4003032 (1977-01-01), Austin et al.
patent: 4969147 (1990-11-01), Markkula et al.
patent: 5008902 (1991-04-01), Key et al.
patent: 5507040 (1996-04-01), Eaton et al.
patent: 5561693 (1996-10-01), Yung et al.
patent: 5724389 (1998-03-01), Marko et al.

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