Automatic assignment of I/O addresses in a computer system

Boots – shoes – and leggings

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39580001, 395828, 395830, 395821, 395823, 364DIG1, G06F 1200

Patent

active

057873062

ABSTRACT:
A peripheral device, connected to an address bus, which has yet to be assigned an I/O address has a pin connected to a configuration select output of a control logic circuit (or a CPU). The peripheral device is reset upon start-up of the system and is not yet required to respond to normal bus accesses or traffic. The CPU analyzes the available addresses in the address space and selects an available I/O address for assignment to that peripheral device. In one embodiment, the CPU then sends a serial bit stream containing the selected I/O address to that peripheral device over a configuration select line. In another embodiment, the CPU asserts a configuration select signal to the peripheral device. The CPU then transmits the selected I/O address to the peripheral device on the address bus. The transmitted I/O address is then stored in the peripheral device, and the device will now respond to this I/O address during subsequent operation of the system. In this way, the peripheral device is assigned an I/O address prior to that device having to interact or become active on the address bus or in the I/O address space.

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PCI Specification Revision 2.0, PCI Local bus, PCI Press Edition, pp. 56-64.
Sebastien Tyrrell et al., "Dynamic Software Configuration Control In Telecommunications Systems," Proceedings of the Fifth RACE TMN Conference, pp. 1-14.

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