Automatic alignment of macro cells

Details Automatic alignment of macro cells Automatic alignment of macro cells

2008-09-23

2011-12-27

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S118000, C716S120000

Reexamination Certificate

active

08086985

ABSTRACT:
In a particular embodiment, a method is disclosed that includes detecting a first pitch between at least two lines (e.g. a power line and a ground line) of a first reference macro. The method also includes generating a virtual grid based on the first pitch and aligning at least a second macro to the virtual grid.

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International Search Report and Written Opinion—PCT/US2009/057440—International Search Authority—European Patent Office, Jan. 11, 2010.
Sapatnekar S. S., et al., “Congestion-Aware Topology Optimization of Structured Power/Ground Networks,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, IEEE Service Center, Piscataway, NJ, US, vol. 24, No. 5, May 1, 2005, pp. 683-695, XP011130814.
Singh J., et al., “A fast Algorithm for power grid design,” Proceedings of the International Symposium on Physical Design—Proceedings of ISPD ' May 2005 International Symposium on Physical Design 2005 Association For Computing Machinery US, 2005, pp. 70-77, XP002561674.
Singh J., et al., “Partition-based Algorithm for Power Grid Design Using Locality,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE, USA, vol. 25, No. 4, Apr. 2006, pp. 664-677, XP002561675.
International Search Report and Written Opinion—PCT/US2009/057440—International Search Authority—European Patent Office, Jan. 11, 2010.
Sapatnekar S. S., et al., “Congestion-Aware Topology Optimization of Structured Power/Ground Networks,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, IEEE Service Center, Piscataway, NJ, US, vol. 24, No. 5, May 1, 2005, pp. 683-695, XP011130814.
Singh J., et al., “A fast Algorithm for power grid design,” Proceedings of the International Symposium on Physical Design—Proceedings of ISPD ' May 2005 International Symposium on Physical Design 2005 Association For Computing Machinery US, 2005, pp. 70-77, XP002561674.
Singh J., et al., “Partition-based Algorithm for Power Grid Design Using Locality,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE, USA, vol. 25, No. 4, Apr. 2006, pp. 664-677, XP002561675.

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