Television – Image signal processing circuitry specific to television – Gray scale transformation
Reexamination Certificate
1998-08-24
2001-04-17
Hsia, Sherrie (Department: 2614)
Television
Image signal processing circuitry specific to television
Gray scale transformation
C348S689000, C348S572000
Reexamination Certificate
active
06219107
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to control methods for automatic gain control circuits in video decoders.
Background: Composite Video
The satisfactory reproduction of a picture requires the transmission of several types of information combined into a single waveform called a composite video signal. The signal is composed of video information and synchronizing information. Composite video describes a signal in which luminance, chrominance, and synchronization information are multiplexed in the frequency, time, and amplitude domain for a single-wire distribution. The luminance is defined as the component signal in color video systems that represents the brightness of the image. Chrominance is defined as the component signal in color video systems that describe color-difference information.
The video signal conveys information concerning the blanking level, the black reference level, average scene brightness level, picture details, and color values. The video signal is unipolar with one direct current (“DC”) level (nominally 0 volts) representing black, and a second level (nominally +700 mV) representing white. Any level between 0 and 700 mV represents a degree of gray.
The synchronizing information consists of horizontal and vertical scanning synchronization, and chrominance decoder synchronization. The horizontal and vertical synchronization information is used to trigger the horizontal and vertical deflection circuits in the receiver. The horizontal sync tells the display where to put the video signal in the left-right dimension, and the vertical sync tells the display where to put the signal in the top-bottom dimension. It consists of pulses having a specific amplitude, duration, and shape best suited to the task at hand. The synchronizing pulses are unipolar with a reference level of 0 V and a peak negative level of nominally −300 mV.
The video signal waveform, with a nominal peak-to-peak amplitude of 700 mV, and the synchronizing signal waveform, with a nominal peak-to-peak amplitude of 300 mV, are added together to form a composite video signal of 1 V peak-to-peak. The synchronizing pulses are placed in parts of the composite signal that do not contain active picture information. These parts are blanked (forced below a black level) to render invisible the retrace of scanning beams on a correctly adjusted display.
These standard video signal levels apply to both conventional television scanning standards—National Television System Committee (“NTSC”) and Phase Alternating Line (“PAL”). The U.S standard is NTSC which uses 525 lines at 60 Hz, while PAL is predominant in Europe and uses 625 lines at 50 Hz. Composite video signals are expressed in IRE units. An IRE unit is defined as one-hundredth of the excursion from the blanking level (0 IRE units) to the reference white level (100 IRE units). A standard 1 V peak-to-peak signal is said to have an amplitude of 140 IRE units of which 100 IRE units are luminance, and 40 IRE units are synchronization information. Further discussion of video circuits and signals can be found in the following texts: M. Robin, DIGITAL TELEVISION FUNDAMENTALS, McGraw-Hill (1998); K. Jack, VIDEO DEMYSTIFIED, 2nd Edition, Harris Semiconductor (1996); and A. Inglis, VIDEO ENGINEERING, 2nd Edition, McGraw-Hill (1996), all of which are hereby incorporated by reference.
Background: Video Decoders
When decoding composite video signals, the input analog video signal is DC-restored to ground during the horizontal sync time, setting the “sync tip” to a zero value. The sync tip is that part of the sync signal (most negative level) which is used as a reference point when handling the video signal (see FIG.
2
). Automatic gain control (“AGC”) is used to keep the output signal of the circuit constant as the input video signal amplitude varies. When a single-ended input (the signal swings relative to a ground) is converted to a differential signal, an internal voltage bias is required. (The differential mode of operation has the advantage of rejection of common-mode signals such as power supply noise and other interferences.) The differential input signal swings about an internal voltage bias which is equal to approximately one-half the input signal peak-to-peak amplitude. The bias voltage must vary as the input amplitude varies. Error in the bias voltage contributes to error in the offset of the AGC output which translates into an undesirable sync tip level. When the signal is amplified by the AGC circuit, a calibration phase for the AGC is employed to compensate for bias voltage errors affecting the output of the analog-to-digital (“A2D”) converter.
Automatic AGC Bias Voltage Calibration in Video Decoder
The present application discloses a method for automatic calibration of AGC bias voltage in a differential video decoder by intermittently applying the unfiltered differential signal directly to the A2D to obtain calibration values. A calibration sequence is performed when a loss of lock to horizontal sync occurs or when perhaps a channel has been changed. A microprocessor connected to the video decoder circuit determines the gain and offset based upon pixel samples obtained from the sync tip and “back porch,” and feeds back the adjusted values to the analog circuit. (The back porch, labelled by “C” in
FIG. 2
, defines another reference level, and is that level from the sync pulse to the start of the active video information.) During calibration, the AGC outputs are linked directly to the A2D inputs. After the calibration process, the A2D input is switched back to receive the filtered differential signal. The gain and bias voltages are then adjusted to compensate for the gain and offset errors in the filters, and to achieve the desired sync tip height and back porch pixel levels at the A2D output.
An advantage is that the calibration feature is automatically controlled using a microprocessor. Another advantage is that performing calibration of bias voltage in the AGC circuit after acquisition of a lock to the horizontal sync, compensates for any error in the internal voltage reference and DAC output, resulting in yield enhancement.
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Mangelsdorf et al., “A CMOS Front-End for CCD Cameras,” 1996 IEEE International Solid-State Circuits Conference, Session 11, Electronics Imaging Circuits, Paper FA 11.5, pp. 186-187, 441.
Alrutz et al., “A Single Chip Video Front End Decoder,” IEEE Transactions on Consumer Electronics, vol. 39, No. 3, Aug. 1993, pp. 489-495.
Redman-White et al., “An Analog CMOS Front-End for a D2-MAC TV Decoder,” IEEE Journal of Solid-State Circuits, vol. 29, No. 8, Aug. 1994, pp. 998-1001.
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J.J. Rijns, “CMOS Low-Distortion High-Frequency Variable-Gain Amplifier,” IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 1029-1034.
Siniscalchi et al, “High-Precision, Programmable 1-10MHz Bandwidth, 0-20dB Gain Communication Channel for Digital Video Applications,” IEEE 1996 Custom Inegrated Circuits Conference, pp. 85-88.
Ganesan Apparajan
Renner Karl H.
Brady III Wade James
Hsia Sherrie
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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