Automatic adjustment of the amplitudes of plural-phase CCD clock

Details Automatic adjustment of the amplitudes of plural-phase CCD clock Automatic adjustment of the amplitudes of plural-phase CCD clock

1982-09-28

1985-06-18

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Charge transfer device

Direction and/or path flow control

307304, 357 24, 377 63, G11C 1928

Patent

active

045244502

ABSTRACT:
In a plural-level gate metallization CCD shift register the clocking voltages applied to the levels are automatically supplied differential offset biases to cause the potential wells to have uniform depth. The differential offset biases are developed responsive to the differences in the threshold voltages of insulated-gate field effect transistors integrated on the same semiconductor substrate as the CCD shift register so as to have their gate electrodes in the different levels of gate metallization.

REFERENCES:
patent: 4138666 (1979-02-01), Eichelberger et al.
patent: 4180807 (1979-12-01), Eichelberger et al.
patent: 4206372 (1980-06-01), Levine
patent: 4223234 (1980-09-01), Levine
patent: 4285000 (1981-08-01), Deyhimy et al.
Kent, "Charge Distribution in Buried-Channel Charge-Coupled Devices" Bell System Tech. Journal, vol. 52, No. 6, Jul.-Aug., 1973, pp. 1009-1025.

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