Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-07-17
2007-07-17
Lam, David (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233100, C365S194000
Reexamination Certificate
active
11301040
ABSTRACT:
An automatic ATD control circuit operates with a first delay circuit accepting a system clock pulse as an input and producing a delayed version of the system clock pulse as an output. The delay to the system clock is performed to allow a frequency comparison in a later part of the circuit. An edge detection circuit operates when the delayed system clock is received and senses an edge of the delayed system clock pulse. A pulse output from the edge detection circuit feeds into a second delay circuit; the second delay circuit produces an output pulse where a period of the pulse is determined by delay characteristics of the sense amplifier and is thus independent of system clock frequency. The pulse is compared to the system clock frequency. If the system clock frequency is above a determined frequency, the automatic ATD control circuit is disabled.
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patent: 5371709 (1994-12-01), Fisher et al.
patent: 5493533 (1996-02-01), Lambrache
patent: 5682353 (1997-10-01), Eitan et al.
patent: 5740112 (1998-04-01), Tanaka et al.
patent: 7002857 (2006-02-01), Kang
Atmel Corporation
Lam David
Schneck Thomas
Schneck & Schneck
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