Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1999-07-13
2001-11-27
Boudreau, Leo (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
Reexamination Certificate
active
06324298
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to defect inspection systems for the semiconductor industry. More particularly, the present invention relates to an automated defect inspection system for patterned wafers, whole wafers, sawn wafers such as on film frames, JEDEC trays, Auer boats, die in gel or waffle packs, multi-chip modules often referred to as MCMs, etc. that is specifically intended and designed for second optical wafer inspection for such defects as metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, and bump or bond pad area defects such as gold or solder bump defects or similar interconnect defects. Specifically, the present invention is an automated defect inspection system for integrated circuits, LCD panels with photolithography circuitry embedded therein, etc. where the system is used as follows: the system is trained by viewing a plurality of known good die under an imaging head resulting in a good die model, an inspection recipe is inputted into the system to define inspection parameters, defect inspection occurs where die are loaded onto, aligned in and viewed by an imaging head for defects in comparison to the good die model, an optional review of the identified defects may occur, and the user may optionally receive or export a report thereon.
2. Background Information
Over the past several decades, the semiconductor has exponentially grown in use and popularity. The semiconductor has in effect revolutionized society by introducing computers, electronic advances, and generally revolutionizing many previously difficult, expensive and/or time consuming mechanical processes into simplistic and quick electronic processes. This boom in semiconductors has been fueled by an insatiable desire by business and individuals for computers and electronics, and more particularly, faster, more advanced computers and electronics whether it be on an assembly line, on test equipment in a lab, on the personal computer at one's desk, or in the home electronics and toys.
The manufacturers of semiconductors have made vast improvements in end product quality, speed and performance as well as in manufacturing process quality, speed and performance. However, there continues to be demand for faster, more reliable and higher performing semiconductors.
One process that has evolved over the past decade or so is the semiconductor inspection process. The merit in inspecting semiconductors throughout the manufacturing process is obvious in that bad wafers may be removed at the various steps rather than processed to completion only to find out a defect exists either by end inspection or by failure during use.
A typical example of the semiconductor manufacture process is summarized as follows. Bare whole wafers are manufactured. Thereafter, circuitry is created on the bare whole wafers. The whole wafer with circuitry is then sawn into smaller pieces known in the industry as die. Thereafter, the die are processed, as is well known in the art, typically as die in waffle and/or gel packs or on substrates.
Today, it is well known that various inspection processes occur during this semiconductor process. Bare wafer inspection may occur on bare whole wafers not long after initial creation from sand and/or after polishing of the wafer but always prior to the deposit of any layers that form the circuitry. Defects being inspected for during bare wafer inspection include surface particulates and surface imperfections or irregularities.
During the deposition of layers, that is the circuit building, on the whole wafer, one or more first optical inspections may occur. First (1
st
) optical inspection is “in process” inspection of wafers during circuitry creation. This 1
st
inspection may be after each layer is deposited, at certain less often intervals, or only once during or after all deposits. This 1
st
optical inspection is usually a sub-micron level inspection in the range of 0.1 micron to <1 micron. This process is used to check for mask alignment or defects such as extra metal, missing metal, contaminants, etc. This 1
st
inspection occurs during circuitry development on the wafer.
Once the whole wafers are at least fully deposited on, that is all of the circuitry is created thereon, a post 1
st
(or 1.5) inspection occurs on the fully processed whole wafers. Generally, this is prior to the deposit of a passivation layer although it need not be. In addition, this post 1st inspection is generally prior to electrical testing or probing of the whole wafers. This inspection is typically a 0.5 micron to 1 micron optical inspection.
After the whole wafers are fully processed, one or more 2
nd
optical inspections are performed. Front end 2
nd
optical inspections occur after the whole wafers are fully processed and, if probing is necessary, just before or right after this probing or electrical testing to determine the quality of the devices. Back end 2
nd
optical inspections occur at various stages such as during the applying of bumps to the die or wafer, during or after sawing of the wafers into sawn wafers, during or after dicing of the wafers, during or after picking up and placing of the die onto other packages such as trays or waffle or gel packs, during or after placing of the wafers onto a substrate, etc. This 2
nd
optical inspection is generally at a 1+ micron level and is generally looking for defects such as metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, and probe or bond pad area defects.
After actual packaging, 3
rd
optical inspections occur. This packaging involves at least one of the following: placing the die on a substrate, wire bonding the die, connecting the leads, attaching the balls to a flip chip, etc. At this point, the inspection involves inspecting the ball grid array, lead straightness, wire bonding, ink marking, and for any package defects such as chips, cracks and voids. This 3
rd
level inspection is generally at a 5+ micron level.
The focus of the semiconductor inspection industry has been bare wafer and 1st optical inspection. Numerous market leaders have developed, patented, and are manufacturing and marketing 1
st
optical inspection systems to perform these inspections including ADE, KLA, Tencor, Inspex, Applied, Orbit and others.
Often this equipment is very expensive and large. At the 1
st
inspection stage, this expense and machine size issue is not as significant as at later inspection stages because only a relatively few parties manufacture the silicon wafers and thus need to inspect bare wafers in comparison to the vast number of companies that buy bare or sawn wafers and further process them into finished chips. These often expensive and large inspection devices are not cost justifiable for smaller shops and as such, inspection equipment is needed that satisfies this need at the 2
nd
and 3
rd
stages as well as is more economical for the vast many smaller companies that finish process wafers.
To a lesser extent, some resources have been spent on 3
rd
optical inspection and several companies including STI, View Engineering, RVSI, and ICOS have developed systems for this purpose and are marketing those systems.
However, none of these systems address the particular and unique constraints of 2
nd
optical and this area has been largely ignored. In actual application, 2
nd
optical inspection has been marginally performed by manual inspection using humans and microscopic equipment. This manual process is inaccurate due to various factors including stress, eye fatigue and boredom of the operator as well as different perceptions by different operators as to the significance of a finding. In addition, smaller circuit geometry and higher throughput requirements are increasing the demands on semiconductor inspection at this 2
nd
optic
Harless Mark
O'Dell Jeffrey
Verburgt Thomas
August Technology Corp.
Boudreau Leo
Vasuta John M.
Werner Brian P.
LandOfFree
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