Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-14
2001-03-20
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220
Reexamination Certificate
active
06205056
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to floating gate memory devices such as an array of Flash electrically, erasable programmable read-only memory (EEPROM) cells. More particularly, it relates to a reference cell trimming verify circuit and method for use in an array of Flash EEPROM memory cells for performing a program verify operation on a reference cell so as to reduce overall testing time during a production process.
As is generally well known in the art, electrical programmable and erasable memory array devices using a floating gate for the storage of charges thereon (Flash EPROMs/EEPROMs) have emerged in recent years. In a conventional EEPROM memory device, a plurality of one-transistor memory cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally within the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
In order to program the EEPROM cell, the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example, the drain region has applied thereto a voltage of approximately +5.0 volts with the control gate having a voltage of approximately +8.5 volts applied. These voltages produce “hot electrons” which are accelerated across the thin dielectric layer and onto the floating gate. This hot electron injection results in an increase of the threshold of the device by approximately two to four volts.
In order to erase the EEPROM cell, a relatively high positive potential (e.g., +5.0 volts) is applied to the source region. The control gate has applied thereto a negative voltage of −8.5 volts, and the drain region is allowed to float. A strong electric field develops between the floating gate and the source region, and negative charges are extracted from the floating gate to the source region by way of Fowler-Norheim tunneling.
In order to determine whether the EEPROM cell has been programmed or not, the magnitude of the read current is measured. Typically, in the read mode of operation, the source region is held at a ground potential and the control gate is held at a potential of about +4.2 volts. The drain region is held at a potential between 1 to 2 volts. Under these conditions, an unprogrammed or erased cell (storing a logic “1”) will conduct a predetermined amount of current. On the other hand, the programmed cell (storing a logic “0”) will have considerably less current flowing.
In addition, in conjunction with the performing of program, erase, and read operations in the array of Flash EEPROM memory cells there is required the task of trimming (program) and verify the threshold of a reference cell from an erased state up to a desired level for the read, erase verify, and program verify modes of operation. This procedure of reference cell trimming and verify are very difficult and time-consuming and are performed by production engineers during the fabrication process of the Flash memory devices. Initially, the reference cell is erased and then it is trimmed and verified. First, high voltage pulses with a controlled pulse width and voltage amplitude are applied to the control gate and the drain of the reference cell above the potential applied to the source. These pulses are applied so as to add charges onto the floating gate of the reference cell. Then, a test mode of operation is performed to verify the threshold voltage V
t
of the reference cell. In this test mode of operation, a fixed gate voltage is applied to the reference cell and a small drain voltage of +0.5 volts is applied to the drain thereof. Under this bias condition, the reference cell will conduct a certain amount of current. This is very similar to the conventional read operation.
If the reference cell has reached the desired program threshold under this bias condition, then a fixed amount of drain current will be known to be flowing which can be determined by laboratory experimentation. In other words, when the voltage at the drain is fixed, for example, at +0.5 volts and an overdrive voltage defined by (V
gs
−V
t
) applied to the control gate is set to 1 volt, a certain desired drain current should be obtained such as 4.5 &mgr;A. However, taken into consideration of the variations caused by the test fixture and changes in the power supply voltage, the actual drain current may be 4.5 &mgr;A±1 &mgr;A or between the range of 3.5 &mgr;A to 5.5 &mgr;A.
If the measured current is higher than 5.5 &mgr;A, then another program pulse will be applied so as to raise the threshold voltage V
t
in order to reduce the overdrive voltage. On the other hand, if the measured current is less than 3.5 &mgr;A, then this means that the reference cell has been over-programmed (e.g., the threshold voltage V
t
is too high). Thus, the reference cell must be erased in order to lower its threshold voltage V
t
. This cycle of program pulse, program verify, program pulse is repeated over and over until the reference cell has successfully been programmed to the desired threshold. Presently, all of the threshold voltages of the reference cells are being trimmed and verified externally with a test fixture. This requires a large amount of time and increases labor costs.
Moreover, it is very difficult to precisely measure the current to be within the desired range during the production process. Further, it is extremely hard to be able to control precisely the amplitude of the program pulse as well as its pulse width. Nevertheless, in order to simplify the production process, the inventor of the present invention has developed a way of implementing the same function on the same semiconductor integrated circuit containing the memory device. This is accomplished by the provision of a reference cell trimming verify circuit for performing a program verify operation on a reference cell so as to reduce overall testing time during a production process, assuming that each on-chip programming pulse can increment the threshold voltage of the reference cell by a finite step. Thus, in order to program a reference cell there will be required many programming pulses. The reference cell trimming verify circuit of the present invention provides the same degree of accuracy as previously obtained by the production engineers.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a reference cell trimming verify circuit and method for use in an array of Flash EEPROM memory cells for performing a program verify operation on a reference cell which has been traditionally unavailable.
It is an object of the present invention to provide a reference cell trimming verify circuit and method for use in an array of Flash EEPROM memory cells for performing a program verify operation on a reference cell so as to reduce overall testing time during a production process.
It is another object of the present invention to provide a reference cell trimming verify circuit and method for use in an array of Flash EEPROM memory cells for performing a program verify operation on a reference cell which is formed on the same semiconductor integrated circuit containing the memory device.
It is still another object of the present invention to provide a reference cell trimming verify circuit and method for use in an array of Flash EEPROM memory cells for performing a program verify operation on a reference cell which includes a reference current branch for generating a reference current, a drain current branch for generating a drain current, and a comparator for comparing the drain current and the reference current in order to determine when the desired threshold voltage of the reference cell has been reached.
In a
Bill Colin S.
Pan Feng
Advanced Micro Devices , Inc.
Chin Davis
Zarabian Amir
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