Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-08-23
2011-08-23
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C716S116000, C716S117000, C716S132000, C716S133000, C716S139000, C700S001000, C700S200000, C700S220000, C717S124000, C717S139000, C717S140000
Reexamination Certificate
active
08006204
ABSTRACT:
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
REFERENCES:
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5563987 (1996-10-01), Scott
patent: 5748875 (1998-05-01), Tzori
patent: 5781763 (1998-07-01), Beukema et al.
patent: 5819050 (1998-10-01), Boehling et al.
patent: 5854929 (1998-12-01), Van Praet et al.
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5867400 (1999-02-01), El-Ghoroury et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5896521 (1999-04-01), Shackleford et al.
patent: 5918035 (1999-06-01), Van Praet et al.
patent: 5964861 (1999-10-01), Gabzdyl et al.
patent: 5999734 (1999-12-01), Willis et al.
patent: 6006022 (1999-12-01), Rhim et al.
patent: 6052518 (2000-04-01), Shigeta et al.
patent: 6101592 (2000-08-01), Pechanek et al.
patent: 6115034 (2000-09-01), Tanaka et al.
patent: 6148374 (2000-11-01), Pawlowski
patent: 6166728 (2000-12-01), Haman et al.
patent: 6182206 (2001-01-01), Baxter
patent: 6195593 (2001-02-01), Nguyen
patent: 6477683 (2002-11-01), Killian et al.
patent: 6618854 (2003-09-01), Mann
patent: 6839889 (2005-01-01), Liu
patent: 0 743 599 (1996-11-01), None
patent: 10-187484 (1998-07-01), None
patent: WO 99/00731 (1999-01-01), None
Freericks, “The nML Machine Description Formalism” (Bericht 1991/15 pp. 3-41).
Fauth et al. Describing instruction set processors using nML (Proc. Euro. Design & Test Conf. Paris Mar. 1995, IEEE 1995, 5 pp.).
Hadjiyiannis et al. “ISDL: an instruction set description language for retargetability” DAC '97, Anaheim California, 1997 ACM 0-89791-920-3/97/06.
Leupers et al. “Retargetable Code Generation Based on Structural Processor Descriptions” (Design Automation for Embedded Systems, vol. 3, No. 1, Jan. 1998, pp. 1-36.
Zivojnovic et al. “DSP Processor/Compiler Co-Design: a quantitative approach” (9thInt'l Symposium on System Synthesis (ISSS '96), Nov. 6-8, 1996, San Diego, CA.
Fauth et al., “Generation of hardware machine models from instruction set descriptions,”VLSI Signal Processing VI, 1993, Workshop on Veldhoven, Netherlands, 20-22, Oct. 1993, New York NY, USA, IEEE Oct. 20, 1993 pp. 242-250.
Hartoog et al. “Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign” (ACM, Jun. 1997, pp. 303-306.
Internet Publication http://www.retarget.com/brfchschk.html (19 pp. undated).
Internet Publication http://www.synopsys.com/products/designware/8051—ds.html (8pp. undated).
Internet Publication http://www.synopsys.com/oruducts/designware/dwpci—ds.html (16 pp. undated).
Internet Publication http://www.lexra.com/product.html (11 pp. undated).
Internet Publication http://www.risccores.com/html/body—aboutarc.htm (13 pp. undated).
Tensilica “Xtensa” Instruction Set Architecture (ISA) Ref. Manual. Rev. 1.0, Tensilica, Inc.
Fauth, A., et al., “Describing Instruction Set Processors Using nML,” IEEE, p. 503-507, (1995).
Hartoog, Mark R., et al., “Generation of Software Tools from Processor Descriptions for Hardware/Software Co-design,” 34th Design Automation Conference (DAC), p. 1-4, (1997).
Akaboshi, et al., “Study on Design Support for Computer Architecture”,Design Automation, 68-7, 13 pages (Oct. 28, 1993).
Fauth, et al., “Describing Instruction Set Processors Using nML”,Proc. EP Design and Test Conf., Parish, Mar. 1995, 5 pages.
Hadjiyiannis, G., et al., “ISDL: An Instruction Set Description Language for Retargetability”, Jun. 9, 1997, 4 pages.
Hakata, et al., “A Software Development Took Generator for ASIC CPU”,Design Automation, 62-25, May 18, 1992, pp. 144-147.
Hikichi, et al.,, “Compilers for Embedded System”,Tech. Report of IEICE, Apr. 1998, 13 pages.
Ohtsuki, et al., “HW/SW Co-Design System PEAS-II for VLIW Processor”,DA Symposium, Jul. 1998, 7 pages.
Sato, et al., “Implementation and Evaluation of PEAS: Practical Environment for ASIP Development”,Design Automation, 64-11, Oct. 23, 1992, pp. 79-86.
Shiomi, et al., “Proposal of Co-Design Workbench PEAS-III for ASIP Design”,Design Automation, 76-10, Jul. 20, 1995, pp. 73-80.
Clucas, R., “Designing with a Customisable Microprocessor Core”, Electronic Engineering, vol. 71, No. 865, Feb. 1, 1999, p. 35.
Nurprasetyo, et al., “Soft-Core Processor Architecture for Embedded System Design”, IEICE Trans. on Electronics, Electronics Soc., vol. E81-C, No. 9, Sep. 1, 1998, pp. 1416-1423.
Sato, et al., “PEAS-1: A hardware/Software Codesign System for ASIP Development”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Engineering Sciences Soc., vol. E77-A, No. 3, Mar. 1, 1994, pp. 483-491.
Shackleford, et al., “Satsuki: An Integrated Processor Synthesis and Compiler Generation System”, IEICE Trans. on Information and Systems, Information and Society; vol. E79-D, No. 10, Oct. 1, 1996, pp. 1373-1381.
Yang, et al., “MetaCore: An Application specific DSP Development System”, Design Automation Conf., 1998, Proc. San Francisco, CA , Jun. 15-19, 1998, IEEE, Jun. 15, 1998, pp. 800-803.
Dixit Ashish B.
Gonzalez Ricardo E.
Killian Earl A.
Lam Monica
Lichtenstein Walter D.
Do Thuan
Nguyen Nha T
Pillsbury Winthrop Shaw & Pittman LLP
Tensilica, Inc.
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