Automated optimization of hierarchical netlists

Details Automated optimization of hierarchical netlists Automated optimization of hierarchical netlists

1993-03-31

1999-09-21

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 1750

Patent

active

059562579

ABSTRACT:
A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.

REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 4967367 (1990-10-01), Piednoir
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5168455 (1992-12-01), Hooper
patent: 5202841 (1993-04-01), Tani
patent: 5210700 (1993-05-01), Tom
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5301318 (1994-04-01), Mittal
patent: 5311443 (1994-05-01), Crain et al.
patent: 5325309 (1994-06-01), Halaviati et al.
patent: 5402357 (1995-03-01), Schaefer et al.
patent: 5426591 (1995-06-01), Ginetti et al.
patent: 5461576 (1995-10-01), Tsay et al.
Daniel Weise, "Multilevel Verification of MOS Circuit", IEEE Trans. on Computer Design, vol. 9, No. 4, pp. 341-351, Apr. 1990.
Synopsys Design Compiler Technical Data Sheet, Version 1.3, 1990.
Primitive Model Description Cell User Guide, Compass Design Automation, V8R3,1991.
Volker Henkel and Ulrich Golzc, "A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification Based on Interaction Rule," IEEE, 1988 Custon Integrated Circuits Conference, pp. 7-4-1-7-4-4.

Affiliated with

Also associated with

Rating

Automated optimization of hierarchical netlists does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automated optimization of hierarchical netlists, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automated optimization of hierarchical netlists will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-86398