Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-02-02
2003-05-27
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S942000
Reexamination Certificate
active
06569692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to an automated method of controlling photoresist develop time to control critical dimensions, and system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
, such as doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped-polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode
14
has a critical dimension
12
, i.e., the width of the gate electrode
14
, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modem semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor
10
depicted in
FIG. 1
, are formed above a semiconducting substrate. In general, semiconductor processing involves, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., must be formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in modern integrated circuit devices. For example, gate electrodes may now be patterned to a width
12
that is approximately 0.2 &mgr;m (2000 Å), and further reductions are planned in the future. As stated previously, the width
12
of the gate electrode
14
corresponds approximately to the channel length
13
of the transistor
10
when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Moreover, it is also desirable that manufacturing operations produce such features in a consistent, reliable and predictable manner. That is, it is desirable that features be formed in a manner such that there is little variation in final feature sizes; despite forming millions of such features on different substrates using different process tools to form such features.
In modern semiconductor fabrication facilities, a variety of factors may tend to cause variations in the size of fabricated structures or features, as compared to the intended or design size of those features. For example, photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above a layer of material that is desired to be patterned using the patterned photoresist layer as a mask. In general, the pattern desired to be formed in the underlying layer of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist reflecting the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer.
One problem that exists with existing photolithography processes is that, at the point in the process where the photoresist is developed, the desired dimensions of the feature formed in the layer of photoresist may be changed or eroded due to excessive time in the develop bath and/or variations in the chemistry used in the bath, etc. The problem may cause features in the underlying process layer to also be formed at dimensions that are different from those anticipated by the design process. For example, in forming line-type features, e.g., a gate electrode, excessive consumption of the feature formed in the layer of photoresist may lead to devices with gate electrodes having critical dimensions that are too small. While such a situation may, at least theoretically, increase the operating speed of the transistor by reducing the channel length, such a reduced size may also result in increased leakage currents and excessive power consumption, both of which are undesirable in modern integrated circuit devices. With respect to hole-type features, such excessive consumption results in holes in the process layer being formed to dimensions greater than anticipated by the design process. This may also be problematic given the densely packed nature of semiconductor devices.
Given the continual reduction of feature sizes in modern integrated circuit devices, it continues to be very important that feature sizes be defined as accurately as possible, and that such processes be repeatable. Thus, a need exists for a method and system that allows for automated control of the formation of critical feature dimensions in modern integrated circuit devices. The present invention is directed to a method and system that solves, or reduces, some or all of the aforementioned problems.
SUMMARY OF
Bode Christopher A.
Hewett Joyce S. Oey
Advanced Micro Devices , Inc.
Brophy Jamie L.
Williams Morgan & Amerson
Zarabian Amir
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