Boots – shoes – and leggings
Patent
1995-04-24
1996-10-08
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364490, 364491, H01L 2500
Patent
active
055638007
ABSTRACT:
A logic synthesis unit generates configuration data of a virtual logic circuit composed of virtual elements, or logic gates each of which carries only a functional definition, in order to realize a logic circuit functional description fed through an input unit. A logic transformation unit, referring to a standard cell library, performs the allocation of real elements for implementation to respective virtual elements to transform the virtual logic circuit into a real logic circuit having the same function as the virtual logic circuit. Then the logic transformation unit, referring to a timing analysis unit, selects a particular real element with a smallest driving capacity from among the real elements in the library performing the same function as an object virtual element and satisfying both fan-out restrictions and delay constraints, and allocates the real element thus selected to the virtual element. Configuration data of the resulting real logic circuit are output in the forms of circuit diagrams, real element connection information lists, and the like through an output unit.
REFERENCES:
patent: 4584653 (1986-04-01), Chih et al.
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4896272 (1990-01-01), Kurosawa
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 5043914 (1991-08-01), Nishiyama et al.
patent: 5197015 (1993-03-01), Hartog et al.
patent: 5282147 (1994-01-01), Goetz et al.
Chowdhry et al., "Minimal Area Design of Power/Ground Nets Having Graph Topologies", IEEE Transactions on Circuits and Systems, vol. CAS-34, No. 12, Dec. 1987, pp. 1441-1451.
Dutta et al., "Automatic Sizing of Power/Ground (P/G) Networks in VLSI", 26th ACM/IEEE Design Automation Conf., 1989, pp. 783-786.
Syed et al., "Single Layer Routing of Power and Ground Networks in Integrated Circuits", Journal of Digital Systems, vol. 6, No. 1, 1982, pp. 53-63.
Ruehli et al., "Analytical Power/Timing Optimization Technique for Digital System" 14th DAC, 1977, pp. 142-146.
Rothermel et al., "Computation of Power Supply Nets in VLSI Layout", 18th Design Automation Conf., 1981, pp. 37-42.
Mennecier et al., "Extension of a Compilable Cell Library with Functionalities Concerning Numerical Processing of Floating Point Data", Euro Asic '92, 1992, pp. 78-82.
Matsumoto Noriko
Nishiyama Tamotsu
Matsushita Electric - Industrial Co., Ltd.
Teska Kevin J.
Walder, Jr. Stephen J.
LandOfFree
Automated logic circuit design system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automated logic circuit design system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automated logic circuit design system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-62024