Automated load determination for partitioned simulation

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 944

Patent

active

060092491

ABSTRACT:
A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist. While constructing the netlist, instances are checked for directives. The directives indicate that the instance should be tracked as a load circuit. For the instances having such a directive, their nets are flagged and the hierarchal portion of the circuit attached to the flagged nets is flattened. The resulting flat circuit replaces the instance in the netlist as a load circuit.

REFERENCES:
patent: 4878179 (1989-10-01), Larsen et al.
patent: 5043914 (1991-08-01), Nishiyama et al.
patent: 5222030 (1993-06-01), D'Angelo et al.
patent: 5249133 (1993-09-01), Batra
patent: 5278769 (1994-01-01), Bair et al.
patent: 5301318 (1994-04-01), Mittal
patent: 5463563 (1995-10-01), Bair et al.
patent: 5471398 (1995-11-01), Stephens
patent: 5473546 (1995-12-01), Filseth
patent: 5481473 (1996-01-01), Kim et al.
patent: 5526277 (1996-06-01), Dangelo et al.
patent: 5548524 (1996-08-01), Hernandez et al.
patent: 5550714 (1996-08-01), Nishiyama
patent: 5553008 (1996-09-01), Huang et al.
patent: 5586319 (1996-12-01), Bell
patent: 5606518 (1997-02-01), Fang et al.
Modeling Strategy for Post Layout Verification, Navabi and Huang, Jun. 1990, pp. 7.1-7.4.
Concurrency Preserving Partitioning (CPP) for Parallel Logic Simulation, Kim and Jean, Jul. 1996, pp. 98-105.
Incorporating the DC Load Flow Model in the Decomposition-Simulation Method of Multi-Area Reliability Evaluation, Mitra and Singh, Aug. 1996, pp. 1245-1253.
Sekine, M., et al., "An Advanced Design System: Design Capture, Functional Test Generation, Mixed Level Simulation and Logic Synthesis (VLSI)", IEEE Proceedings of IEEE Custom Integrated Circuits Conference, 19.4.1-19.4.6, (1989).
"DC and Transient Output Variables.", HSPICE User's Manual, vol. 3, Meta-Software, Inc., HSPICE Version H92,, pp. 4-16-4-18, (1992).
"Probing Subcircuit Currents.", ADM User's Guide, Version 1.5, ADS Software, Inc., pp. 4-5-4-7, (Feb. 1995).
Engel, T.G., "Splice: A New Analytical Network Analysis Software", IEEE, pp. 2c6.17-2c6.19, (1995).
Frezza, S.T., et al., "SPAR: A Schematic Place and Route System", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12, 7, 956-973, (1993).
Harrington, B.K., "SPIL--A Program to Automatically Create ASIC Macro Models for Logic Simulation", IEEE, pp. p5-5.1-p5.5.4, (1990).
Pavan, P., et al., "A Complete Radiation Reliability Software Simulator", IEEE Transactions on Nuclear Science, vol. 41, No. 6, pp. 2619-2630, (Dec. 1994).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Automated load determination for partitioned simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automated load determination for partitioned simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automated load determination for partitioned simulation will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2388452

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.