Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2002-03-07
2004-03-09
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S058000, C361S111000
Reexamination Certificate
active
06704179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD) protection circuits and, more particularly, to an automated computer aided design (CAD) system for automatically designing ESD circuits for a given application.
2. Description of the Related Art
As electronic components are getting smaller and smaller along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity, even at levels which can neither be seen nor felt. Electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials (voltages), caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry. Device failures are not always immediately catastrophic. Often the device is only slightly weakened but is less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components. Various considerations are necessary for ESD protection circuits. For example, ESD protection circuits for input nodes must also support quality dc, ac, and RF model capability in order to co-design ESD circuits for analog and RF circuits. With the growth of the high-speed data rate transmission, optical interconnect, wireless and wired marketplaces, the breadth of applications and requirements is broad. Each type of application space has a wide range of power supply conditions, number of independent power domains, and circuit performance objectives. As a result, an ESD design system which has dc and RF characterized models, design flexibility, automation, ESD characterization, and satisfies digital, analog and RF circuits is required to design and co-synthesize ESD needs of mixed signal RF technology.
Much effort has been expended by industry to protect electronic devices from ESD damage. Traditionally, ESD designs are custom designed using graphical systems. ESD ground rules and structures are typically built into the designs requiring a custom layout. This has lead to custom design for digital products such as DRAMs, SRAMs, microprocessors, ASIC development and foundry technologies. This design practice does not allow for the flexibility needed for RF applications. A difficulty in the design of RF ESD solutions is that traditionally, specific designs are fixed in size in order to achieve verifiable ESD results for a technology. The difficulty with analog and RF technology is that a wide range of circuit applications exists where one ESD size structure is not suitable due to loading of the circuit. A second issue is that the co-synthesis of the circuit and the circuit must be done to properly evaluate the RF performance objectives. RF characterization of the network that is flexible with the device size is important for the evaluation of the tradeoffs of RF performance and ESD. A third issue for RF mixed signal designs, there are analog and digital circuits. In these environments, there are some products which primarily use digital CMOS circuits and some which are bipolar dominated. In this environment, some applications prefer CMOS-based ESD networks, and others are motivated to use Bipolar-based ESD networks.
SUMMARY OF THE INVENTION
it is therefore an object of the present invention to provide an automated ESD design system which eliminates the need to custom build ESD circuits for each new application.
The present invention provides an ESD CAD strategy that provides design flexibility, RF characterization and models of ESD elements, automation, and choice of ESD network type. The present invention uses a hierarchical system of parametrized cells, herein after referred to a “p-cells”, which are constructed into higher level ESD networks. Lowest order p-cells are RF and dc characterized. ESD verification, dc characterization, schematics and LVS are completed on the higher order circuits. RF characterization can be done on the lowest level pcell circuits or higher level pcell circuits.
Diode, bipolar and MOSFET hierarchical cells were used to establish both CMOS MOSFET-based ESD networks and SiGe bipolar-based networks. The parametrized cells, or “p-cells”, can be constructed in a commercially available CAD software environment such a CADENCE, (Registered Trademark) design system to form a kit. Ones of the p-cells are “growable” elements such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. The p-cells fix some variables, and pass some variables to the higher order p-cell circuits through inheritance. From base p-cells, ESD circuits are constructed for input pads, VDD-to-VSS power clamps, VSS-to-VSS power clamps, and VCC-to-VDD power clamps. In these categories, there exists both the CMOS-based and the BiCMOS SiGe-based implementations.
The ESD design system allows for change of circuit topology as well as structure size in an automated fashion. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit. The circuit topology automation allows for the customer to autogenerate new ESD circuits and ESD power clamps without additional design work. Interconnects and wiring between the circuit elements are also autogenerated. This automation allows for size (spatial) variables, product application variables and ESD protection levels data to achieve either area requirements, product specifications or ESD objectives.
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Francisco H. de la Moneda, et al., “Hybrid Protective Device for MOS-LSI Chips”, IEEE Transactions on Parts, Hybrids, and Packaging, vol. PHP-12, No. 3, Sep. 1976.
Jackson Stephen W.
Kotulak Richark
McGuireWoods LLP
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