Automated error detection for multiple block memory array chip a

Details Automated error detection for multiple block memory array chip a Automated error detection for multiple block memory array chip a

1988-06-02

1990-04-17

Atkinson, Charles E.

Excavating

371 401, G06F 1110

Patent

active

049186922

ABSTRACT:
A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking devices. By previously blowing out any of the linking devices in each address changing system, an externally applied address signal is changed with another address signal to be applied to a corresponding memory cell array block.

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IBM J. Res. Develop.: "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review", by C. L. Chen et al., V. 28, No. 2, 3/84, pp. 124-134.

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