Automated circuit tester

Excavating

Patent

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Details

371 27, G01R 3128

Patent

active

046047441

ABSTRACT:
An automated integrated circuit tester is constructed as a state machine. Complete test routines are contained in a state memory. A state generator is controlled by state memory and produces addresses therefor. A complete test condition can be set up using the information in a single address in state memory. Provisions are made for test routine loading from a local computer, which also serves to log data without interfering in test execution. A preferred embodiment provides both DC parametric and AC testing in a tester which can accomodate up to 256 pins. A single force and measure unit is devoted to each pin.

REFERENCES:
patent: 3969618 (1976-07-01), Strubel et al.
patent: 4287594 (1981-09-01), Shirasaka
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 4348759 (1982-09-01), Schnurmann
patent: 4365334 (1982-12-01), Smith et al.
patent: 4439858 (1984-03-01), Petersen
patent: 4450560 (1984-05-01), Conner
patent: 4493079 (1985-01-01), Hughes, Jr.
patent: 4517661 (1985-05-01), Graf et al.

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