Automated bottom-up and top-down partitioned design synthesis

Details Automated bottom-up and top-down partitioned design synthesis Automated bottom-up and top-down partitioned design synthesis

2003-03-13

2011-12-20

Shah, Kamini S (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S015000, C716S105000

Reexamination Certificate

active

08082138

ABSTRACT:
An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

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patent: 6711729 (2004-03-01), McElvain et al.

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